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參數(shù)資料
| 型號(hào)： | AD7008PCB |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | CMOS DDS Modulator |
| 中文描述： | 的CMOS DDS調(diào)制器 |
| 文件頁(yè)數(shù)： | 3/16頁(yè) |
| 文件大?。?/td> | 505K |
| 代理商： | AD7008PCB |
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AD7008
REV. B
–3–
TIMING CHARACTERISTICS
(V
AA
= V
DD
+5 V
±
5%; T
A
= T
MIN
to T
MAX
, unless otherwise noted)
AD7008AP20
Typ
AD7008JP50
Typ
Parameter
Min
Max
Min
Max
Units
Test Conditions/Comments
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
t
16
t
17
t
18
t
19
t
20
50
20
20
5
3
4t
1
2t
1
5
5
10
10
20
10
3
3
20
8
8
10
10
20
8
8
5
3
4t
1
2t
1
5
5
10
10
20
10
3
3
20
8
8
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLOCK Period
CLOCK High Duration
CLOCK Low Duration
CLOCK to Control Setup Time
CLOCK to Control Hold Time
LOAD Period
LOAD High Duration
1
LOAD High to TC0–TC3 Setup Time
LOAD High to TC0–TC3 Hold Time
WR
Falling to
CS
Low Setup Time
WR
Falling to
CS
Low Hold Time
Minimum
WR
Low Duration
Minimum
WR
High Duration
WR
to D0–D15 Setup Time
WR
to D0–D15 Hold Time
SCLK Period
SCLK High Duration
SCLK Low Duration
SCLK Rising to SDATA Setup Time
SCLK Rising to SDATA Hold Time
NOTE
1
May be reduced to 1t
1
if LOAD is synchronized to CLOCK and Setup (t
4
) and Hold (t
5
) Times for LOAD to CLOCK are observed.
D0–D15
VALID DATA
CS
WR
t
11
t
10
t
12
t
15
t
13
t
14
Figure 3. Parallel Port Timing
SCLK
DB31
SDATA
DB0
t
20
t
16
t
17
t
19
t
18
Figure 4. Serial Port Timing
Figure 2. Register Transfer Timing
LOAD
TC0–TC3
VALID
t
9
t
8
t
6
t
7
CLOCK
FSEL, LOAD,
TC3–TC0
VALID
VALID
t
1
t
3
t
4
t
5
t
2
Figure 1. Clock Synchronization Timing
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