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參數(shù)資料
| 型號(hào)： | AD7008PCB |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | CMOS DDS Modulator |
| 中文描述： | 的CMOS DDS調(diào)制器 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 505K |
| 代理商： | AD7008PCB |
START 0 Hz
VBW 10 kHz
STOPST 5.6 SEC
REF 5.0 dBm
RANGE 5.0 dBm
OFFSE–54.7 dB
Figure 29. f
CLK
= 50 MHz, f
OUT
= 9.1 MHz
START 0 Hz
VBW 10 kHz
STOPST 5.6 SEC
REF 5.0 dBm
RANGE 5.0 dBm
OFFSET–54.1 dB
CENTERBW 3 kHz
VBW 10 kHz
SPANST 5.6 SEC
REF 5.0 dBm
RANGE 5.0 dBm
OFFSET–47.0 dB
Figure 31. f
CLK
= 50 MHz, f
OUT
= 13.1 MHz
Figure 30. f
CLK
= 50 MHz, f
OUT
= 11.1 MHz
CENTERBW 3 kHz
VBW 10 kHz
SPANST 5.6 SEC
REF 5.0 dBm
RANGE 5.0 dBm
OFFSE–44.8 dB
130
50
50
70
60
10
0
90
80
100
110
120
40
30
20
MASTER CLOCK – MHz
T
A
D
Figure 32. f
CLK
= 50 MHz, f
OUT
= 16.5 MHz
Figure 33. Typical Current Consumption vs. Frequency
Figure 34. Typical Plot of SFDR vs. Master Clock Frequency
When f
OUT
= 1/3f
CLK
, Frequency Word = 5671C71C Hex
–40
–75
50
–60
–70
10
–65
0
–45
–55
–50
40
30
20
MASTER CLOCK – MHz
W
REV. B
–14–
AD7008–Typical Performance Characteristics
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