參數(shù)資料
型號： AD6816
廠商： Analog Devices, Inc.
英文描述： Interface For ATM User-Network Interface IC to Category #5 Unshielded Twisted Pair (UTP) system or a fiber optic system.(ATM用戶網(wǎng)絡(luò)接口與#5類非屏蔽雙絞線系統(tǒng)或其他光纖系統(tǒng)的接口芯片)
文件頁數(shù)： 19/20頁
文件大?。?/td> 483K
代理商： AD6816
AD6816
–19–
REV. A
SONET/
SDH
FRAMING
SIEMENS
PXB 4240
SDHT
LOCAL
BUS
R
UTOPIA
T
UTOPIA
AD6816
155Mbps UTP#5
INTERFACE IC
T
:
LINE DRIVER
CLOCK GENERATOR
R
:
EQUALIZER
BASELINE
RESTORATION
CLOCK RECOVERY
TRANSMIT CLOCK
TRANSMIT CLOCK
RECEIVE CLOCK
RECEIVE DATA
TRANSMIT DATA
SEGMENTATION
SDH
REASSEMBLY
SIEMENS
PXB 4110
SARE
PCI
BUS
TRANSFORMER
AND
FILTER
OPTICAL
TRANSCEIVER
MODULE
UTP#5
CONNECTOR
Figure 32. NIC Block Diagram: AD6816 with Siemens ATM Chipset
LVDS to PECL Conversion
LVDS levels from the Siemens SDHT can be shifted to PECL
levels to the AD6816 using capacitive coupling (Figure 33).
This scheme assumes the LVDS output drives the “l(fā)ong” portion
of the transmission line. The passive shifting and termination
network is located as close to the PECL input as possible.
AD6816
NOTE:
TO ENSURE PROPER
IMPEDANCE MATCHING,
ALL COMPONENTS SHOULD
BE PLACED AS CLOSE TO THE
AD6816 DESTINATION PINS AS
POSSIBLE.
DRIVEIN
DRIVEINN
1k
1k
10nF
160
470
V
CC
= +5V
100nF
100nF
100
TRANSMISSION LINE
(50
PCB TRACE)
LVDS_OUT
LVDS_OUT
SIEMENS
SDHT
PXB4240
BRIEF ANALYSIS:
1. TERMINATION IS DONE BY THE 100
RESISTOR BETWEEN THE DIFFERENTIAL LINES.
2. THE 100nF CAPACITORS PROVIDE AC COUPLING TO THE SDHT OUTPUT.
3. THE RESISTOR DIVIDER GENERATES THE NEW OFFSET VOLTAGE (VBB, IN CENTER
BETWEEN PECL VIH VIL) OF APPROXIMATELY 3.7V.
4. THE TWO 1k
RESISTORS ARE USED FOR DECOUPLING THE TWO SIGNALS.
5. PECL COMMON-MODE VOLTAGE EXTERNALLY SUPPLIED. COMPONENTS ARE
NOT REQUIRED.
Figure 33. LVDS to PECL Conversion
PECL to LVDS Conversion
PECL levels from the AD6816 can be shifted to LVDS levels to
the Siemens SDHT using either ac coupling or dc coupling
(Figures 34a and 34b). These schemes assume that the PECL
output drives the “l(fā)ong” portion of the transmission line. The
passive shifting and termination network is located as close to
the LVDS input as possible.
NOTE:
TO ENSURE PROPER
IMPEDANCE MATCHING,
ALL COMPONENTS
SHOULD BE PLACED
AS CLOSE TO THE AD6816
DESTINATION PINS AS
POSSIBLE.
1k
1k
10nF
220
120
V
CC
= +3.3V
100nF
100nF
TRANSMISSION LINE
(50
PCB TRACE)
LVDS_IN
LVDS_IN
SIEMENS
SDHT
PXB4240
BRIEF ANALYSIS:
1. TERMINATION IS DONE BY A PARALLEL THEVENIN SCHEME.
2. THE 100nF CAPACITORS PROVIDE AC COUPLING.
3. THE RESISTOR DIVIDER NETWORK FIXES NEW OFFSET VOLTAGE AT 1.2V.
PECL_OUT
PECL_OUT
AD6816
120
120
82
82
V
CC
= +5V
V
CC
= +5V
a.
NOTE:
TO ENSURE PROPER IMPEDANCE
MATCHING, ALL COMPONENTS
SHOULD BE PLACED AS CLOSE TO
THE SDHT DESTINATION PINS
AS POSSIBLE.
82
82
47
0.01μF
TRANSMISSION LINE
(50
PCB TRACE)
LVDS_IN
LVDS_IN
SIEMENS
SDHT
PXB4240
BRIEF ANALYSIS:
1. SHIFTING NETWORK BASED ON THEVENIN SCHEME WITH LOWER RESISTOR
REPLACED BY DIVIDER.
2. COMMON MODE VOLTAGE TRANSFORMED FROM 3.7V DOWN TO 1.4V.
3. DIFFERENTIAL VOLTAGE SWING ATTENUATED FROM 600mV MINIMUM (PECL)
TO 220mV MINIMUM FOR LVDS.
PECL_OUT
PECL_OUT
82
82
47
AD6816
FERRITE BEAD
+5V
PECL 5V (V
CC
)
b.
Figure 34. PECL to LVDS Conversion
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