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參數(shù)資料
| 型號： | AD6816 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Interface For ATM User-Network Interface IC to Category #5 Unshielded Twisted Pair (UTP) system or a fiber optic system.(ATM用戶網(wǎng)絡接口與#5類非屏蔽雙絞線系統(tǒng)或其他光纖系統(tǒng)的接口芯片) |
| 文件頁數(shù)： | 11/20頁 |
| 文件大?。?/td> | 483K |
| 代理商： | AD6816 |
AD6816
–11–
REV. A
PECL Output Compatibility with ATM User–Network
Interface IC Inputs
The PECL outputs (RXCLKOUT/N, RXDATAOUT/N) are
more than adequate for driving UNI IC PECL inputs. A focus
on PECL output specifications and on UNI IC PECL input dc
characteristics, given below, demonstrates this.
The PECL output levels, specified in single-ended terms over
0
°
C to +70
°
C (V
OH
and V
OL
), should not be taken at face value.
Since the output signals that V
OH
and V
OL
refer to are differen-
tially processed (typical UNI IC “self-biased” PECL Inputs re-
quire ac coupling), the differential voltage swing between V
OH
and V
OL
determine compatibility. Simply combining the V
OH
MIN
specification with the V
OL
MAX
specification, however, confuses
a compatibility analysis since both V
OH
and V
OL
track with tem-
perature. This means V
OH
MIN
and V
OL
MAX
do not occur simul-
taneously, but at opposite temperature extremes (refer to Figure
20). Note that the differential voltage swing (V
OH
–V
OL
) remains
> 0.93 V over temperature.
Test results of identical PECL outputs over temperature reveal
that minimum differential voltage swings at –40
°
C and at +85
°
C
equal 0.72 V and 0.81 V, respectively (with 6
σ
confidence).
Typical UNI ICs have V
IH MIN
and V
IL MAX
dc specifications that
require differential drive (V
IH MIN
–V
IL MAX
) > 0.4 V. One UNI
IC has V
IH MIN
and V
IL MAX
specifications that require differen-
tial drive > 0.6 V. The AD6816 PECL outputs have the differ-
ential swing (0.72 V minimum) to drive these UNI ICs
comfortably, and with adequate margin.
TEMPERATURE –
°
C
V
0
–1.2
–2.0
–0.2
–1.0
–1.4
–1.8
–0.6
–0.8
–1.6
–0.4
–60
140
–40
–20
0
20
40
60
80
100
120
V
OH
MIN
V
OL
MAX
0.93V
0.94V
V
OH
V
OL
Figure 20. PECL Output Levels–Simulation Graph
Figure 21. Evaluation/Test Circuit Assembly Drawing
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