參數(shù)資料
型號: AD6655BCPZ-801
廠商: Analog Devices, Inc.
英文描述: IF Diversity Receiver
中文描述: IF分集接收機
文件頁數(shù): 16/84頁
文件大?。?/td> 2012K
代理商: AD6655BCPZ-801
AD6655
Rev. 0 | Page 16 of 84
t
PD
t
DCO
t
H
t
S
CLK+
DECIMATED
INTERLEAVED
CMOS DATA
CHANNEL B:
DATA
CHANNEL A:
DATA
CHANNEL B:
DATA
CHANNEL B:
DATA
CHANNEL A:
DATA
CHANNEL B:
FD BITS
CHANNEL A:
FD BITS
CHANNEL B:
FD BITS
CHANNEL B:
FD BITS
CHANNEL A:
FD BITS
DECIMATED
INTERLEAVED
FD DATA
DECIMATED
DCO
CHANNEL A:
DATA
CHANNEL A:
FD BITS
0
Figure 4. Decimated Interleaved CMOS Mode Data and Fast Detect Output Timing
t
PD
t
DCO
t
H
t
S
CLK+
DECIMATED
CMOS IQ
OUTPUT DATA
CHANNEL A/B:
I DATA
CHANNEL A/B:
Q DATA
CHANNEL A/B:
Q DATA
CHANNEL A/B:
I DATA
CHANNEL A/B:
Q DATA
CHANNEL A/B:
FD BITS
CHANNEL A/B:
FD BITS
CHANNEL A/B:
FD BITS
CHANNEL A/B:
FD BITS
CHANNEL A/B:
FD BITS
CMOS FD
DATA
DECIMATED
DCOA/DCOB
CHANNEL A/B:
I DATA
CHANNEL A/B:
FD BITS
0
Figure 5. Decimated IQ Mode CMOS Data and Fast Detect Output Timing
t
PD
t
DCO
CLK–
CLK+
LVDS
DATA
CHANNEL A:
DATA
CHANNEL B:
DATA
CHANNEL A:
DATA
LVDS
FAST DET
DCO–
DCO+
CHANNEL B:
DATA
CHANNEL A:
FD
CHANNEL B:
FD
CHANNEL A:
FD
CHANNEL B:
FD
CHANNEL A:
DATA
CHANNEL A:
FD
0
Figure 6. Decimated Interleaved LVDS Mode Data and Fast Detect Output Timing
t
SSYNC
t
HSYNC
SYNC
CLK+
0
Figure 7. SYNC Timing Inputs
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