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參數(shù)資料
| 型號(hào)： | AD6620PCB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 65 MSPS Digital Receive Signal Processor |
| 中文描述： | 65 MSPS的數(shù)字接收信號(hào)處理器 |
| 文件頁數(shù)： | 5/43頁 |
| 文件大小： | 354K |
| 代理商： | AD6620PCB |
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AD6620
–5–
REV. 0
TIMING CHARACTERISTICS
(C
LOAD
= 40 pF All Outputs)
Test
Level
AD6620AS
Min
Parameter (Conditions)
Temp
Typ
Max
Units
CLK Timing Requirements:
t
CLK
t
CLKL
t
CLKH
Reset Timing Requirements:
t
RESL
Input Data Timing Requirements:
t
SI
Input
1
to CLK Setup Time
t
HI
Input
1
to CLK Hold Time
Parallel Output Switching Characteristics:
t
DPR
CLK to OUT[15:0] Rise Delay
t
DPF
CLK to OUT[15:0] Fall Delay
t
DPR
CLK to DV
OUT
Rise Delay
t
DPF
CLK to DV
OUT
Fall Delay
t
DPR
CLK to I
QOUT
Rise Delay
t
DPF
CLK to I
QOUT
Fall Delay
t
DPR
CLK to A
BOUT
Rise Delay
t
DPF
CLK to A
BOUT
Fall Delay
SYNC Timing Requirements:
t
SY
SYNC
2
to CLK Setup Time
t
HY
SYNC
2
to CLK Hold Time
SYNC Switching Characteristics:
t
DY
CLK to SYNC
3
Delay Time
Serial Input Timing:
t
SSI
SDI to SCLK
t
Setup Time
t
HSI
SDI to SCLK
t
Hold Time
t
HSRF
SDFS to SCLK
u
Hold Time
t
SSF
SDFS to SCLK
t
Setup Time
4
t
HSF
SDFS to SCLK
t
Hold Time
4
Serial Frame Output Timing:
t
DSE
SCLK
u
to SDFE Delay Time
t
SDFEH
SDFE Width High
t
DSO
SCLK
u
to SDO Delay Time
SCLK Switching Characteristics, SBM = “1”
:
t
SCLK
SCLK Period
3
t
SCLKL
SCLK Width Low
t
SCLKH
SCLK Width High
t
SCLKD
CLK to SCLK Delay Time
S
erial Frame Timing
,
SBM = “1”
:
t
DSF
SCLK
u
to SDFS Delay Time
t
SDFSH
SDFS Width High
SCLK Timing Requirements, SBM
=
“0”
:
t
SCLK
SCLK Period
t
SCLKL
SCLK Width Low
t
SCLKH
SCLK Width High
CLK Period
CLK Width Low
CLK Width High
Full
Full
Full
I
IV
IV
15.4
7.0
7.0
ns
ns
ns
0.5
×
t
CLK
0.5
×
t
CLK
RESET
Width Low
Full
I
30.0
ns
Full
Full
IV
IV
–1.0
6.5
ns
ns
Full
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
IV
IV
8.0
7.5
6.5
5.5
7.0
6.0
7.0
5.5
19.5
19.5
19.0
11.5
19.5
13.5
19.5
13.5
ns
ns
ns
ns
ns
ns
ns
ns
Full
Full
IV
IV
–1.0
6.5
ns
ns
Full
V
7.0
23.5
ns
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
1.0
2.0
4.0
1.0
2.0
ns
ns
ns
ns
ns
Full
Full
Full
IV
V
IV
3.5
11.0
ns
ns
ns
t
SCLK
4.5
11.0
Full
Full
Full
Full
I
V
V
V
2
×
t
CLK
ns
ns
ns
ns
0.5
×
t
SCLK
0.5
×
t
SCLK
6.5
13.0
Full
Full
IV
V
1.0
4.0
ns
ns
t
SCLK
Full
Full
Full
I
IV
IV
15.4
0.4
×
t
SCLK
0.4
×
t
SCLK
ns
ns
ns
0.5
×
t
SCLK
0.5
×
t
SCLK
NOTES
1
Specification pertains to: IN[15:0], EXP[2:0], A/B.
2
Specification pertains to: SYNC_NCO, SYNC_CIC, SYNC_RCF.
3
SCLK period will be
≥
2
×
t
CLK
when AD6620 is Serial Bus Master (SBM = 1) depending on the SDIV word.
4
SDFS setup and hold time must be met, even when configured as outputs, since internally the signal is sampled at the pad.
Specifications subject to change without notice.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD6620AS | 65 MSPS Digital Receive Signal Processor |
| AD6620S | 65 MSPS Digital Receive Signal Processor |
| AD6620 | 65 MSPS Digital Receive Signal Processor(采樣速率65MSPS的數(shù)字接收信號(hào)處理器) |
| AD6622AS | Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6622PCB | Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD6620S | 制造商:AD 制造商全稱:Analog Devices 功能描述:65 MSPS Digital Receive Signal Processor |
| AD6620S/PCB | 制造商:Analog Devices 功能描述:DUAL CHANNEL DECIMATING RECEIV 制造商:Analog Devices 功能描述:SGNL PROCESSOR 169CSPBGA - Bulk |
| AD6622 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6622AS | 制造商:Analog Devices 功能描述:Transmit Signal Processor 128-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:4 CHANNEL 65 MSPS DIGITAL UPCONVERTER - Bulk |
| AD6622PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
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