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| 型號(hào)： | AD640JP-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP LOG 2.3MA 20PLCC |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 放大器類型： | 對(duì)數(shù) |
| 電路數(shù)： | 1 |
| -3db帶寬： | 350MHz |
| 電流 - 輸入偏壓： | 7µA |
| 電壓 - 輸入偏移： | 50µV |
| 電流 - 電源： | 35mA |
| 電流 - 輸出 / 通道： | 2.3mA |
| 電壓 - 電源，單路/雙路(±)： | ±4.5 V ~ 7.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 20-PLCC（9x9） |
| 包裝： | 帶卷 (TR) |
AD640
REV. C
–15–
diminishes the risk of instability due to poor grounding. Never-
theless, it must be remembered that at high frequencies even
very small lengths of wire, including the leads to capacitors,
have significant impedance. The ground plane itself can also
generate small but troublesome voltages due to circulating cur-
rents in a poor layout. A printed circuit evaluation board is
available from Analog Devices (Part Number ADEB640) to
facilitate the prototyping of an application using one or two
AD640s, plus various external components.
At very low signal levels various effects can cause significant
deviation from the ideal response, apart from the inherent non-
linearities of the transfer function already discussed. Note that
any spurious signal presented to the AD640s is demodulated and
added to the output. Thus, in the absence of thorough shielding,
emissions from any radio transmitters or RFI from equipment
operating in the locality will cause the output to appear too
high. The only cure for this type of error is the use of very care-
ful grounding and shielding techniques.
50 MHz–150 MHz Converter with 70 dB Dynamic Range
Figure 30 shows a logarithmic converter using two AD640s
which can provide at least 70 dB of dynamic range, limited
mostly by first stage noise. In this application, an rf choke (L1)
prevents the transmission of dc offset from the first to the sec-
ond AD640. One or two turns in a ferrite core will generally
suffice for operation at frequencies above 30 MHz. For ex-
ample, one complete loop of 20 gauge wire through the two
holes in a Fair-Rite type 2873002302 core provides an inductance
of 5
H, which presents an impedance of 1.57 k at 50 MHz.
The shunting effect across the 150
differential impedance at
the signal interface is thus fairly slight.
The signal source is optionally terminated by R1. To minimize
the input offset voltage R2 should be chosen to match the dc
resistance of the terminated source. (However, the offset voltage
is not a critical consideration in this ac-coupled application.)
Note that all unused inputs are grounded; this improves the
isolation from the outputs back to the inputs.
A transimpedance op amp (U3, AD844) converts the summed
logarithmic output currents of U1 and U2 to a ground referenced
voltage scaled 1 V per decade. The resistor R5 is nominally 1 k
but is increased slightly to compensate for the slope deficit at the
operating frequency, which can be determined from Figure 12.
The inverting input of U3 forms a virtual ground, so that each
logarithmic output of U1 and U2 is loaded by 100
(R3 or
R4). These resistors in conjunction with capacitors C1 and C2
form independent low-pass filters with a time constant of about
INPUT LEVEL – dBm IN 50
0
–60
–50
–40
–30
–20
–10
0
+1
–1
ERROR
–
dB
4
1
0
–70
LOW-PASS
FILTERED
OUTPUT
–
V
2
3
Figure 31. Logarithmic Output and Nonlinearity for Circuit
of Figure 30, for a Sine Wave Input at f = 80 MHz
5 ns. These capacitors should be connected directly across Pins
13 and 14, as shown, to prevent high frequency output currents
from circulating in the ground plane. A second 5 ns time con-
stant is formed by feedback resistor R5 in conjunction with the
transcapacitance of U3.
This filtering is adequate for input frequencies of 50 MHz or
above; more elaborate filtering can be devised for pulse
applications requiring a faster rise time. In applications where
only a long term measure of the input is needed, C1 and C2 can
5k
0.1 F
+15V
–15V
TO U3
AND U4
15
13
14
16
19
18
17
11
12
20
6
8
7
5
3
4
9
1
2
10
SIG
+IN
ATN
OUT
CKT
COM
RG1 RG0 RG2 LOG
OUT
LOG
COM
+VS SIG
+OUT
SIG
–IN
ATN
LO
ATN
COM
BL1
BL2
ITC
–VS
SIG
–OUT
1k
ATN
COM
ATN
IN
U2 AD640
C6
0.1 F
68
+6V
68
R7
3.3M
1/2
AD712
DENOTES A CONNECTION TO THE GROUND PLANE;
OBSERVE COMMON CONNECTIONS WHERE SHOWN.
ALL UNMARKED CAPACITORS ARE 0.1 F CERAMIC.
OFFSET
NULLING
FEEDBACK
U4a
5k
SIGNAL INPUT
15
13
14
16
19
18
17
11
12
20
SIG
+IN
ATN
OUT
CKT
COM
RG1 RG0 RG2 LOG
OUT
LOG
COM
+VS SIG
+OUT
SIG
–IN
ATN
LO
ATN
COM
BL1
BL2
ITC
–VS
SIG
–OUT
1k
ATN
COM
ATN
IN
U1 AD640
6
8
7
5
3
49
12
10
C1
(SEE
TEXT)
C2
(SEE
TEXT)
C7
4.7 F
C8
4.7 F
1
2
3
B
OFFSET
NULLING
FEEDBACK
U4b
7
6
5
A
1/2
AD712
1/2
AD712
U3a
1
2
3
NC
R2
50k
R3
50k
U3b
1/2
AD712
7
6
5
R4
200k
R5
200k
LOG
OUTPUT
+100mV/dB
C4
4.7 F
R1
49.9
C3
100 F
C5
0.1 F
A
B
+15V
–15V
TO U1
AND U2
TO U3
AND U4
9.1V
+6V
–6V
18
–6V
18
NC = NO CONNECT
R6
3.3M
Figure 32. Complete 95 dB Dynamic Range Converter
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| AD640JPZ | 功能描述:IC AMP LOG 2.3MA 20PLCC RoHS:是 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 其它有關(guān)文件:TS1854A View All Specifications 標(biāo)準(zhǔn)包裝:50 系列:- 放大器類型:通用 電路數(shù):4 輸出類型:滿擺幅 轉(zhuǎn)換速率:0.25 V/µs 增益帶寬積:630kHz -3db帶寬:- 電流 - 輸入偏壓:16nA 電壓 - 輸入偏移:1000µV 電流 - 電源:162µA 電流 - 輸出 / 通道:48mA 電壓 - 電源，單路/雙路(±):1.8 V ~ 6 V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SO 包裝:管件 |
| AD640JPZ-REEL7 | 功能描述:IC AMP LOG 2.3MA 20PLCC RoHS:是 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 標(biāo)準(zhǔn)包裝:50 系列:- 放大器類型:J-FET 電路數(shù):2 輸出類型:- 轉(zhuǎn)換速率:3.5 V/µs 增益帶寬積:1MHz -3db帶寬:- 電流 - 輸入偏壓:30pA 電壓 - 輸入偏移:2000µV 電流 - 電源:200µA 電流 - 輸出 / 通道:- 電壓 - 電源，單路/雙路(±):7 V ~ 36 V，±3.5 V ~ 18 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 |
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| AD640TCHIPS | 制造商:AD 制造商全稱:Analog Devices 功能描述:DC-Coupled Demodulating 120 MHz Logarithmic Amplifier |
| AD640TD | 制造商:AD 制造商全稱:Analog Devices 功能描述:DC-Coupled Demodulating 120 MHz Logarithmic Amplifier |
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