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參數(shù)資料
| 型號(hào)： | AD5621AKS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 2.7 V to 5.5 V, <100 UA, 8-/10-/12-Bit nanoDAC D/A, SPI Interface, SC70 Package |
| 中文描述： | SERIAL INPUT LOADING, 8 us SETTLING TIME, 12-BIT DAC, PDSO6 |
| 封裝： | PLASTIC, SC-70, MO-203AB, SURFACE MOUNT PACKAGE-6 |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 599K |
| 代理商： | AD5621AKS |
Preliminary Technical Data
AD5601/AD5611/AD5621
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rev. PrC | Page 7 of 20
TOP VIEW
(Not to Scale)
V
DD
GND
SCLK
DIN
AD5601/
AD5611/
AD5621
V
OUT
SYNC
1
2
3
6
5
4
0
Figure 3. 6-Lead SC70 Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
1
SYNC
Function
Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC
goes low, it enables the input shift register, and data is transferred in on the falling edges of the clocks that follow.
The DAC is updated following the 16
th
clock cycle unless SYNC is taken high before this edge, in which case the
rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can
be transferred at rates up to 30 MHz.
Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input.
Power Supply Input. The AD5601/AD5611/AD5621 can be operated from 2.7 V to 5.5 V. V
DD
should be decoupled
to GND.
Ground Reference Point for All Circuitry on the AD5601/AD5611/AD5621.
Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.
2
SCLK
3
DIN
4
V
DD
5
6
GND
V
OUT
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| AD5621BKS | 制造商:AD 制造商全稱:Analog Devices 功能描述:2.7 V to 5.5 V, <100 UA, 8-/10-/12-Bit nanoDAC D/A, SPI Interface, SC70 Package |
| AD5621BKS-U1 | 制造商:Analog Devices 功能描述: |
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