參數(shù)資料
型號(hào)： AD5621AKS
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： 2.7 V to 5.5 V, <100 UA, 8-/10-/12-Bit nanoDAC D/A, SPI Interface, SC70 Package
中文描述： SERIAL INPUT LOADING, 8 us SETTLING TIME, 12-BIT DAC, PDSO6
封裝： PLASTIC, SC-70, MO-203AB, SURFACE MOUNT PACKAGE-6
文件頁(yè)數(shù)： 15/20頁(yè)
文件大?。?/td> 599K
代理商： AD5621AKS
Preliminary Technical Data
AD5601/AD5611/AD5621
AD5601/AD5611/AD5621 to 68HC11/68L11 Interface
Figure 30 shows a serial interface between the AD5601/
AD5611/AD5621 and the 68HC11/68L11 microcontrollers.
SCK of the 68HC11/68L11 drives the SCLK of the AD5601/
AD5611/AD5621, while the MOSI output drives the serial data
line of the DAC. The SYNC signal is derived from a port line
(PC7). The setup conditions for correct operation of this
interface are as follows: the 68HC11/68L11 should be
configured so that its CPOL bit is a 0 and its CPHA bit is a 1.
When data is being transmitted to the DAC, the SYNC line is
taken low (PC7). When the 68HC11/68L11 is configured as
above, data appearing on the MOSI output is valid on the falling
edge of SCK. Serial data from the 68HC11/68L11 is transmitted
in 8-bit bytes with only eight falling clock edges occurring in
the transmit cycle. Data is transmitted MSB first. To load data to
the AD5601/AD5611/AD5621, PC7 is left low after the first
eight bits are transferred, and a second serial write operation is
performed to the DAC. PC7 is taken high at the end of this
procedure.
Rev. PrC | Page 15 of 20
68HC11/
68L11
AD5601/AD5611/
AD5621*
*ADDITIONAL PINS OMITTED FOR CLAIRTY
PC7
SCK
MOSI
SYNC
SCLK
DIN
0
Figure 30. AD5601/AD5611/AD5621 to 68HC11/68L11 Interface
AD5601/AD5611/AD5621 to Blackfin ADSP-BF53X
Interface
Figure 31 shows a serial interface between the AD5601/
AD5611/AD5621 and the Blackfin ADSP-BF53x
microprocessors. The ADSP-BF53x processor family
incorporates two dual-channel synchronous serial ports,
SPORT1 and SPORT0, for serial and multiprocessor
communications. Using SPORT0 to connect to the AD5601/
AD5611/AD5621, the setup for the interface is as follows:
DT0PRI drives the SDIN pin of the AD5601/AD5611/AD5621,
while TSCLK0 drives the SCLK of the part. The SYNC is driven
from TFS0.
ADSP-BF53X
AD5601/AD5611/
AD5621
*ADDITIONAL PINS OMITTED FOR CLAIRTY
DT0PRI
TSCLK0
TFS0
DIN
SCLK
SYNC
0
Figure 31. AD5601/AD5611/AD5621 to Blackfin ADSP-BF53X Interface
AD5601/AD5611/AD5621 to 80C51/80L51 Interface
Figure 32 shows a serial interface between the AD5601/
AD5611/AD5621 and the 80C51/80L51 microcontroller. The
setup for the interface is as follows: TXD of the 80C51/80L51
drives SCLK of the AD5601/AD5611/AD5621, while RXD
drives the serial data line of the part. The SYNC signal is again
derived from a bit programmable pin on the port. In this case,
port line P3.3 is used. When data is to be transmitted to the
AD5601/AD5611/AD5621, P3.3 is taken low. The 80C51/80L51
transmit data only in 8-bit bytes; thus, only eight falling clock
edges occur in the transmit cycle. To load data to the DAC, P3.3
is left low after the first eight bits are transmitted, and a second
write cycle is initiated to transmit the second byte of data. P3.3
is taken high following the completion of this cycle. The 80C51/
80L51 output the serial data in a format that has the LSB first.
The AD5601/AD5611/AD5621 require their data with the MSB
as the first bit received. The 80C51/80L51 transmit routine
should take this into account.
80C51/80L51*
AD5601/AD5611/
AD5621*
*ADDITIONAL PINS OMITTED FOR CLAIRTY
P3.3
TXD
RXD
SYNC
SCLK
DIN
0
Figure 32. AD5601/AD5611/AD5621 to 80C51/80L51 Interface
AD5601/AD5611/AD5621 to MICROWIRE Interface
Figure 33 shows an interface between the AD5601/AD5611/
AD5621 and any MICROWIRE compatible device. Serial data is
shifted out on the falling edge of the serial clock and is clocked
into the AD5601/AD5611/AD5621 on the rising edge of the SK.
MICROWIRE*
AD5601/AD5611/
AD5621*
*ADDITIONAL PINS OMITTED FOR CLAIRTY
CS
SK
SO
SYNC
SCLK
DIN
0
Figure 33. AD5601/AD5611/AD5621 to MICROWIRE Interface
相關(guān)PDF資料
PDF描述
AD5601BKS 2.7 V to 5.5 V, <100 UA, 8-/10-/12-Bit nanoDAC D/A, SPI Interface, SC70 Package
AD5611BKS 2.7 V to 5.5 V, <100 UA, 8-/10-/12-Bit nanoDAC D/A, SPI Interface, SC70 Package
AD5621BKS 2.7 V to 5.5 V, <100 UA, 8-/10-/12-Bit nanoDAC D/A, SPI Interface, SC70 Package
AD5620BRJ-1500RL7 Single, 12-/14-/16-Bit nanoDAC with 5 ppm/C On-Chip Reference in SOT-23
AD5620 Single, 12-/14-/16-Bit nanoDAC with 5 ppm/C On-Chip Reference in SOT-23
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD5621AKSZ 制造商:Analog Devices 功能描述:DAC SGL RES-STRING 12-BIT 6PIN SC-70 - Bulk
AD5621AKSZ-500RL7 功能描述:IC DAC 12BIT V-OUT SC70-6 RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:nanoDAC™ 標(biāo)準(zhǔn)包裝:1 系列:- 設(shè)置時(shí)間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND
AD5621AKSZ-REEL7 功能描述:IC DAC 12BIT 5V MICROPWR SC70-6 RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:nanoDAC™ 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:3,000 系列:nanoDAC™ 設(shè)置時(shí)間:80µs 位數(shù):18 數(shù)據(jù)接口:DSP，MICROWIRE?，QSPI?，串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:SOT-23-8 供應(yīng)商設(shè)備封裝:SOT-23-8 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極 采樣率（每秒）:- 產(chǎn)品目錄頁(yè)面:784 (CN2011-ZH PDF) 配用:EVAL-AD5680EBZ-ND - BOARD EVAL FOR AD5680 其它名稱:AD5680BRJZ-2REEL7TR
AD5621BKS 制造商:AD 制造商全稱:Analog Devices 功能描述:2.7 V to 5.5 V, <100 UA, 8-/10-/12-Bit nanoDAC D/A, SPI Interface, SC70 Package
AD5621BKS-U1 制造商:Analog Devices 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*