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參數(shù)資料
| 型號(hào)： | AD5621AKS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 2.7 V to 5.5 V, <100 UA, 8-/10-/12-Bit nanoDAC D/A, SPI Interface, SC70 Package |
| 中文描述： | SERIAL INPUT LOADING, 8 us SETTLING TIME, 12-BIT DAC, PDSO6 |
| 封裝： | PLASTIC, SC-70, MO-203AB, SURFACE MOUNT PACKAGE-6 |
| 文件頁(yè)數(shù)： | 13/20頁(yè) |
| 文件大小： | 599K |
| 代理商： | AD5621AKS |
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Preliminary Technical Data
AD5601/AD5611/AD5621
GENERAL DESCRIPTION
D/A SECTION
The AD5601/AD5611/AD5621 DAC are fabricated on a CMOS
process. The architecture consists of a string DAC followed by
an output buffer amplifier. Figure 24 is a block diagram of the
DAC architecture.
Rev. PrC | Page 13 of 20
V
DD
V
OUT
GND
RESISTOR
NETWORK
REF (+)
REF (–)
OUTPUT
AMPLIFIER
DAC REGISTER
0
Figure 24. DAC Architecture
Because the input coding to the DAC is straight binary, the ideal
output voltage is given by
×
=
N
DD
OUT
V
D
2
V
where
D
is the decimal equivalent of the binary code that is
loaded to the DAC register.
RESISTOR STRING
The resistor string section is shown in Figure 25. It is simply a
string of resistors, each of value R. The code loaded to the DAC
register determines at which node on the string the voltage is
tapped off to be fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the string
to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
R
R
R
R
R
TO OUTPUT
AMPLIFIER
0
Figure 25. Resistor String Section
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating rail-to-rail
voltages on its output, giving an output range of 0 V to V
DD
. It is
capable of driving a load of 2 k in parallel with 1000 pF to
GND. The source and sink capabilities of the output amplifier
can be seen inFigure 10. The slew rate is 0.5 V/μs, with a half-
scale settling time of 8 μs with the output unloaded.
SERIAL INTERFACE
The AD5601/AD5611/AD5621 have a 3-wire serial interface
(SYNC, SCLK, and DIN) that is compatible with SPI, QSPI, and
MICROWIRE interface standards as well as most DSPs. See
Figure 2 for a timing diagram of a typical write sequence.
The write sequence begins by bringing the SYNC line low. Data
from the DIN line is clocked into the 16-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 30 MHz, making the AD5601/AD5611/AD5621compatible
with high speed DSPs. On the 16
th
falling clock edge, the last
data bit is clocked in and the programmed function is executed
(a change in DAC register contents and/or a change in the
mode of operation). At this stage, the SYNC line might be kept
low or brought high. In either case, it must be brought high for a
minimum of 33 ns before the next write sequence so that a
falling edge of SYNC can initiate the next write sequence.
Because the SYNC buffer draws more current when V
IN
= 1.8 V
than it does when V
IN
= 0.8 V, SYNC should be idled low
between write sequences for even lower power operation of the
part, as mentioned above. However, it must be brought high
again just before the next write sequence.
INPUT SHIFT REGISTER
The input shift register is 16 bits wide (see Figure 26). The first
two bits are control bits that control which mode of operation
the power is in (normal mode or any one of three power-down
modes). For a complete description of the various modes, see
the Power-Down Modes section. The next 16 bits are the data
bits, which are transferred to the DAC register on the 16
th
falling
edge of SCLK.
DATA BITS
DB15 (MSB)
DB0 (LSB)
PD1
PD0
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NORMAL OPERATION
1 k
TO GND
100 k
TO GND
THREE-STATE
POWER-DOWN MODES
0
0
1
1
0
1
0
1
0
Figure 26. Input Register Contents
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| AD5601BKS | 2.7 V to 5.5 V, <100 UA, 8-/10-/12-Bit nanoDAC D/A, SPI Interface, SC70 Package |
| AD5611BKS | 2.7 V to 5.5 V, <100 UA, 8-/10-/12-Bit nanoDAC D/A, SPI Interface, SC70 Package |
| AD5621BKS | 2.7 V to 5.5 V, <100 UA, 8-/10-/12-Bit nanoDAC D/A, SPI Interface, SC70 Package |
| AD5620BRJ-1500RL7 | Single, 12-/14-/16-Bit nanoDAC with 5 ppm/C On-Chip Reference in SOT-23 |
| AD5620 | Single, 12-/14-/16-Bit nanoDAC with 5 ppm/C On-Chip Reference in SOT-23 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD5621AKSZ | 制造商:Analog Devices 功能描述:DAC SGL RES-STRING 12-BIT 6PIN SC-70 - Bulk |
| AD5621AKSZ-500RL7 | 功能描述:IC DAC 12BIT V-OUT SC70-6 RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:nanoDAC™ 標(biāo)準(zhǔn)包裝:1 系列:- 設(shè)置時(shí)間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| AD5621AKSZ-REEL7 | 功能描述:IC DAC 12BIT 5V MICROPWR SC70-6 RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:nanoDAC™ 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:3,000 系列:nanoDAC™ 設(shè)置時(shí)間:80µs 位數(shù):18 數(shù)據(jù)接口:DSP，MICROWIRE?，QSPI?，串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:SOT-23-8 供應(yīng)商設(shè)備封裝:SOT-23-8 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極 采樣率（每秒）:- 產(chǎn)品目錄頁(yè)面:784 (CN2011-ZH PDF) 配用:EVAL-AD5680EBZ-ND - BOARD EVAL FOR AD5680 其它名稱:AD5680BRJZ-2REEL7TR |
| AD5621BKS | 制造商:AD 制造商全稱:Analog Devices 功能描述:2.7 V to 5.5 V, <100 UA, 8-/10-/12-Bit nanoDAC D/A, SPI Interface, SC70 Package |
| AD5621BKS-U1 | 制造商:Analog Devices 功能描述: |
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