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參數(shù)資料
| 型號： | AD5520JSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PPMU SNGL-CH 64-LQFP |
| 標準包裝： | 1 |
| 類型： | 每引腳參數(shù)測量單元（PPMU） |
| 應(yīng)用： | 自動測試設(shè)備 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 775 (CN2011-ZH PDF) |
| 配用： | EVAL-AD5520EBZ-ND - BOARD EVAL FOR AD5520 |
AD5520
Rev. B | Page 15 of 24
FORCE CONTROL AMPLIFIER
The force control amplifier requires external capacitors
connected between the COMPOUTx and COMPINx pins.
For stability with large capacitance at the DUT, the largest
capacitance value (3000 pF) should be selected. The force
control amplifier should always contribute the dominant
pole in the control loop. Settling times increase with
larger capacitances. ACx inputs select which external
compensation capacitor is used.
Table 10. AC0, AC1 Compensation Capacitor Selection
AC0
AC1
Function
Low
Select External Compensation Capacitor 0
High
Low
Select External Compensation Capacitor 1
Low
High
Select External Compensation Capacitor 2
COMPARATOR FUNCTION AND STROBING
The AD5520 has an on-board window comparator that
provides two bits of useful information, DUT too low or
DUT too high. CPSEL is the digital input that controls
this function, selecting whether it should compare to the
voltage sense or the current sense amplifier.
Table 11. Comparator Function Select
CPSEL
Function
Low
Compare CPL, CPH to MEASVOUT
High
Compare CPL, CPH to MEASIOUT
After CPSEL has selected which amplifier output is of interest,
logic input CPCK is used to initiate comparator sampling and
update the logic outputs CPOH and CPOL. This indicates
whether the voltages at MEASIOUT or MEASVOUT have
exceeded voltages set at CPL or CPH (thus providing DUT too
high or DUT too low information). A rising edge on STB is
required to clock the CPOH and CPOL data out.
Table 12. CPCK Synchronous Logic Outputs
CPOH
Function
Low
High
MEASVOUT or MEASIOUT < CPH MEASVOUT or
MEASIOUT > CPH
CPOL
Function
Low
High
MEASVOUT or MEASIOUT > CPL MEASVOUT or
MEASIOUT < CPL
CLAMP FUNCTION
Clamp circuitry, which is also included on-chip, clamps the
force amplifier’s output if the voltage or current applied to the
DUT exceeds the clamp levels, CLL and CLH. The clamp
circuitry also comes into play in the event of a short or open
circuit. When in force current range, the voltage clamps protect
the DUT from an open circuit. Likewise, when forcing a voltage
and a short circuit occurs, the current clamps protect the DUT.
The clamps also function to protect the DUT if a transient
voltage or current spike occurs when changing to a different
operating mode, or when programming the device to a different
current range.
The digital output flags, which indicate a clamp limit has been
hit, are CLHDETECT for the upper clamp, and CLLDETECT
output for the lower clamp.
Table 13. Clamp Detect Outputs
CLHDETECT
Function
Low
Upper Clamp Inactive
High
Upper Clamp Active
CLLDETECT
Function
Low
Lower Clamp Inactive
High
Lower Clamp Active
HIGH CURRENT RANGES
With the use of an external high current amplifier, two high
current ranges are possible. The current range values can be set
as required in the application through appropriate selection of
the sense resistors connected between MEASI5H, MEASI4H,
and MEASIL. When one of these high current ranges (Mode 4
or Mode 5) is selected via the AMx control lines, the appro-
priate QM4 or QM5 output is enabled. As a result, these outputs
can be used to control relays connected in series with the high
current amplifier, as shown in Figure 26.
Table 14. High Current Range Logic Outputs
QM4
QM5
Function
High
Low
Current Range Mode 4 Enable Output
Low
High
Current Range Mode 5 Enable Output
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