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參數(shù)資料
| 型號(hào)： | AD5520JSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 5/24頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PPMU SNGL-CH 64-LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 每引腳參數(shù)測(cè)量單元（PPMU） |
| 應(yīng)用： | 自動(dòng)測(cè)試設(shè)備 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁(yè)面： | 775 (CN2011-ZH PDF) |
| 配用： | EVAL-AD5520EBZ-ND - BOARD EVAL FOR AD5520 |
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AD5520
Rev. B | Page 13 of 24
THEORY OF OPERATION
The AD5520 is a single-channel per pin parametric measure-
ment unit (PPMU) for use in semiconductor automatic test
equipment. It contains programmable modes to force a pin
voltage and measure the corresponding current (FVMI), force
current measure voltage (FIMV), force current measure current
(FIMI), force voltage measure voltage (FVMV), and force
nothing measure voltage (FNMV). The PPMU can force or
measure a voltage from 11 V to +11 V. It can force or measure
currents up to 6 mA using the internal amplifier, while the
addition of an external amplifier enables higher current ranges.
External resistors allow users to choose the optimum ranges for
their needs.
The device provides a force sense capability to ensure accuracy
at the tester pin. A guard output is also available to drive the
shield of a force/sense pair.
The AD5520 has an on-board window comparator that
provides two bits of useful information, DUT too low or too
high. Also provided on the chip is clamp circuitry that flags via
CLHDETECT and CLLDETECT if the voltage applied to FIN
or across the DUT exceeds the voltage applied to CLL and CLH.
On-chip is clamp circuitry that clamps the output of the force
amplifier if the voltage at MEASIOUT and MEASVOUT
exceeds CLL or CLH.
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