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參數(shù)資料
| 型號： | AD5348BRUZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 24/24頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 12BIT OCTAL VOUT 38-TSSOP |
| 產品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 50 |
| 設置時間： | 8µs |
| 位數(shù)： | 12 |
| 數(shù)據接口： | 并聯(lián) |
| 轉換器數(shù)目： | 8 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 8.3mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 38-TFSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 38-TSSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 8 電壓，單極；8 電壓，雙極 |
| 采樣率（每秒）： | 125k |
| 產品目錄頁面： | 782 (CN2011-ZH PDF) |
AD5346/AD5347/AD5348
Rev. 0 | Page 9 of 24
AD5348 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
TOP VIEW
(Not to Scale)
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
AD5348
LDAC
A1
A0
WR
CS
AGND
VOUTD
VREFCD
VREFEF
VREFGH
VOUTC
VOUTB
VOUTA
VREFAB
PD
VDD
DB4
DB5
DB6
CLR
GAIN
DB11
DB10
DB7
DB8
DB9
12-BIT
VOUTH
VOUTG
VOUTF
VOUTE
DGND
A2
RD
BUF
DB2
DB0
DB3
DB1
03331-0-009
Figure 9. AD5348 Pin Configuration—TSSOP
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
40
39
38
37
36
35
34
33
32
31
LDAC
A1
A0
WR
CS
AGND
VOUTD
V
RE
F
CD
V
RE
F
EF
V
RE
F
GH
VOUTC
VOUTB
VOUTA
V
RE
F
AB
PD
V
DD
DB4
DB5
DB6
CLR
GAIN
DB11
DB10
DB7
DB8
DB9
VOUTH
VOUTG
VOUTF
VOUTE
DGND
A2
RD
BUF
AGND
V
DD
TOP VIEW
(Not to Scale)
AD5348
12-BIT
DB
3
DB
2
DB
1
DB
0
03331-0-010
Figure 10. AD5348 Pin Configuration—LFCSP
Table 7. AD5348 Pin Function Descriptions
Pin Number
TSSOP
LFCSP
Mnemonic
Function
1
35
VREFGH
Reference Input for DACs G and H.
2
36
VREFEF
Reference Input for DACs E and F.
3
37
VREFCD
Reference Input for DACs C and D.
4
38, 39
VDD
Power Supply Pin(s). This part can operate from 2.5 V to 5.5 V, and the supply should be decoupled with a
10 F capacitor in parallel with a 0.1 F capacitor to GND. Both VDD pins on the LFCSP package must be at
the same potential.
5
40
VREFAB
Reference Input for DACs A and B.
6–9,
11–14
1–4,
7–10
VOUTX
Output of DAC X. Buffered output with rail-to-rail operation.
10
5, 6
AGND
Analog Ground. Ground reference for analog circuitry.
15
11
DGND
Digital Ground. Ground reference for digital circuitry.
16
12
BUF
Buffer Control Pin. Controls whether the reference input to the DAC is buffered or unbuffered.
17
13
LDAC
Active Low Control Input. Updates the DAC registers with the contents of the input registers, which allows
all DAC outputs to be simultaneously updated.
18
14
A0
LSB Address Pin. Selects which DAC is to be written to.
19
15
A1
Address Pin. Selects which DAC is to be written to.
20
16
A2
MSB Address Pin. Selects which DAC is to be written to.
21–32
17–28
DB0–DB11
Twelve Parallel Data Inputs. DB11 is the MSB of these 12 bits.
33
29
CS
Active Low Chip Select Input. Used in conjunction with WR to write data to the parallel interface, or with
RD to read back data from a DAC.
34
30
RD
Active Low Read Input. Used in conjunction with CS to read data back from the internal DACs.
35
31
WR
Active Low Write Input. Used in conjunction with CS to write data to the parallel interface.
36
32
GAIN
Gain Control Pin. Controls whether the output range from the DAC is 0 V to VREF or 0 V to 2 × VREF.
37
33
CLR
Asynchronous Active Low Control Input. Clears all input registers and DAC registers to zeros.
38
34
PD
Power-Down Pin. This active low control pin puts all DACs into power-down mode.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD5348BRUZRUZ | 制造商:Analog Devices 功能描述:DAC,AD5348B 12bit 8us octal TSSOP |
| AD534J | 制造商:AD 制造商全稱:Analog Devices 功能描述:Internally Trimmed Precision IC Multiplier |
| AD534JD | 功能描述:IC TRIMMED MULTIPLIER/DIV 14-DIP RoHS:否 類別:集成電路 (IC) >> 線性 - 模擬乘法器，除法器 系列:- 標準包裝:25 系列:HA 功能:模擬乘法器 位元/級數(shù):四象限 封裝/外殼:16-CDIP（0.300"，7.62mm） 供應商設備封裝:16-CDIP 側面銅焊 包裝:管件 |
| AD534JD/+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog Multiplier/Divider |
| AD534JDZ | 功能描述:IC MULTIPLIER PREC TRIM 14-CDIP RoHS:是 類別:集成電路 (IC) >> 線性 - 模擬乘法器，除法器 系列:- 標準包裝:25 系列:HA 功能:模擬乘法器 位元/級數(shù):四象限 封裝/外殼:16-CDIP（0.300"，7.62mm） 供應商設備封裝:16-CDIP 側面銅焊 包裝:管件 |
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