參數(shù)資料
型號(hào)： AD5348BRUZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 10/24頁(yè)
文件大?。?/td> 0K
描述： IC DAC 12BIT OCTAL VOUT 38-TSSOP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 50
設(shè)置時(shí)間： 8µs
位數(shù)： 12
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 8
電壓電源： 單電源
功率耗散（最大）： 8.3mW
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 38-TFSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 38-TSSOP
包裝： 管件
輸出數(shù)目和類型： 8 電壓，單極；8 電壓，雙極
采樣率（每秒）： 125k
產(chǎn)品目錄頁(yè)面： 782 (CN2011-ZH PDF)
AD5346/AD5347/AD5348
Rev. 0 | Page 18 of 24
The bias generator, the output amplifier, the resistor string, and
all other associated linear circuitry are all shut down when the
power-down mode is activated. However, the contents of the
registers are unaffected when in power-down. The time to exit
power-down is typically 2.5 s for VDD = 5 V and 5 s when VDD =
3 V. This is the time from a rising edge on the PD pin to when
the output voltage deviates from its power-down voltage. See
SUGGESTED DATA BUS FORMATS
In many applications, the GAIN and BUF pins are hardwired.
However, if more flexibility is required, they can be included in
a data bus. This enables the user to software program GAIN,
giving the option of doubling the resolution in the lower half of
the DAC range. In a bused system, GAIN and BUF may be
treated as data inputs because they are written to the device
during a write operation and take effect when LDAC is taken
low. This means that the reference buffers and the output
amplifier gain of multiple DAC devices can be controlled using
common GAIN and BUF lines. Note that GAIN and BUF are
not read back during an RD operation.
The AD5347 and AD5348 data bus must be at least 10 and 12
bits wide, respectively, and are best suited to a 16-bit data bus
system.
Examples of data formats for putting GAIN and BUF on a
16-bit data bus are shown in Figure 40. Note that any unused
bits above the actual DAC data may be used for GAIN and BUF.
03331-0-048
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
GAIN
X
BUF
X
X = UNUSED BIT
X
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
GAIN
X
BUF
DB11 DB10
AD5347
AD5348
Figure 40. AD5347/AD5348 Data Format for Word Load with
GAIN and BUF Data on 16-Bit Bus
Table 8. AD5346/AD5347/AD5348 Truth Table
CLR
LDAC
CS
WR
RD
A2
A1
A0
Function
1
X
No Data Transfer
1
X
1
X
No Data Transfer
0
X
Clear All Registers
1
0
→1
1
0
Load DAC A Input Register
1
0
→1
1
0
1
Load DAC B Input Register
1
0
→1
1
0
1
0
Load DAC C Input Register
1
0
→1
1
0
1
Load DAC D Input Register
1
0
→1
1
0
Load DAC E Input Register
1
0
→1
1
0
1
Load DAC F Input Register
1
0
→1
1
0
Load DAC G Input Register
1
0
→1
1
Load DAC H Input Register
1
X
0
1
→0
0
Read Back DAC Register A
1
X
0
1
→0
0
1
Read Back DAC Register B
1
X
0
1
→0
0
1
0
Read Back DAC Register C
1
X
0
1
→0
0
1
Read Back DAC Register D
1
X
0
1
→0
1
0
Read Back DAC Register E
1
X
0
1
→0
1
0
1
Read Back DAC Register F
1
X
0
1
1→0
1
0
Read Back DAC Register G
1
X
0
1
→0
1
Read Back DAC Register H
1
0
X
1
X
Update DAC Registers
X
0
X
Invalid Operation
X = Don’t Care
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