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參數(shù)資料
| 型號： | AD5348BRUZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT OCTAL VOUT 38-TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 設(shè)置時間： | 8µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 8 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 8.3mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 38-TFSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 38-TSSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 8 電壓，單極；8 電壓，雙極 |
| 采樣率（每秒）： | 125k |
| 產(chǎn)品目錄頁面： | 782 (CN2011-ZH PDF) |
AD5346/AD5347/AD5348
Rev. 0 | Page 20 of 24
DECODING MULTIPLE AD5346/AD5347/AD5348s
The CS pin on these devices can be used in applications to
decode a number of DACs. In this application, all DACs in the
system receive the same data and WR pulses, but only the CS to
one of the DACs will be active at any one time, so data will only
be written to the DAC whose CS is low.
The 74HC139 is used as a 2-line to 4-line decoder to address
any of the DACs in the system. To prevent timing errors from
occurring, the enable input should be brought to its inactive
state while the coded address inputs are changing state.
Figure 44 shows a diagram of a typical setup for decoding
multiple devices in a system. Once data has been written
sequentially to all DACs in a system, all the DACs can be
updated simultaneously using a common LDAC line. A com-
mon CLR line can also be used to reset all DAC outputs to 0 V.
ENABLE
CODED
ADDRESS
1G
1A
1B
VDD
VCC
74HC139
DGND
1Y0
1Y1
1Y2
1Y3
A0
A1
A2
WR
LDAC
CLR
DATA
INPUTS
DATA
INPUTS
DATA
INPUTS
DATA
INPUTS
DAT
A
BUS
A0
A1
A2
WR
LD AC
CLR
CS
A0
A1
A2
WR
LD AC
CLR
CS
AD5346/AD5347
/AD5348
A0
A1
A2
WR
LD AC
CLR
CS
A0
A1
A2
WR
LD AC
CLR
CS
AD5346/AD5347
/AD5348
AD5346/AD5347
/AD5348
AD5346/AD5347
/AD5348
03331-
0-
027
Figure 44. Decoding Multiple DAC Devices
AD5346/AD5347/AD5348 AS DIGITALLY
PROGRAMMABLE WINDOW DETECTORS
A digitally programmable upper/lower limit detector using two
of the DACs in the AD5346/AD5347/AD5348 is shown in
Figure 45. Any pair of DACs in the device may be used, but for
simplicity the description refers to DACs A and B.
The upper and lower limits for the test are loaded to DACs A
and B which, in turn, set the limits on the CMP04. If a signal at
the VIN input is not within the programmed window, an LED
indicates the fail condition.
5V
GND
VREFAB
VDD
VIN
FAIL
PASS
1k
1k
PASS/
FAIL
1/6 74HC05
1/2
CMP04
VREF
0.1
F
10
F
VOUTB
VOUTA
AD5346/AD5347/
AD5348
03331-
0-
028
Figure 45. Programmable Window Detector
PROGRAMMABLE CURRENT SOURCE
Figure 46 shows the AD5346/AD5347/AD5348 used as the
control element of a programmable current source. In this
example, the full-scale current is set to 1 mA. The output
voltage from the DAC is applied across the current setting
resistor of 4.7 k in series with the 470 adjustment
potentiometer, which gives an adjustment of about ±5%.
Suitable transistors to place in the feedback loop of the ampli-
fier include the BC107 and the 2N3904, which enable the
current source to operate from a minimum VSOURCE of 6 V. The
operating range is determined by the operating characteristics
of the transistor. Suitable amplifiers include the AD820 and the
OP295, both having rail-to-rail operation on their outputs. The
current for any digital input code and resistor value can be
calculated as follows:
mA
R
D
V
G
I
N
REF
)
2
(
×
=
where:
G is the gain of the buffer amplifier (1 or 2).
D is the digital input code.
N is the DAC resolution (8, 10, or 12 bits).
R is the sum of the resistor plus adjustment potentiometer in k.
VDD = 5V
5V
LOAD
VSOURCE
EXT
REF
GND
VOUT
4.7k
470
*ONLY ONE CHANNEL OF VREF AND VOUT SHOWN
0.1
F
0.1
F
10
F
VIN
GND
AD5346/AD5347/
AD5348
VDD
VREF*VOUT*
03331-0-029
Figure 46. Programmable Current Source
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參數(shù)描述 |
|---|---|
| AD5348BRUZRUZ | 制造商:Analog Devices 功能描述:DAC,AD5348B 12bit 8us octal TSSOP |
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| AD534JD | 功能描述:IC TRIMMED MULTIPLIER/DIV 14-DIP RoHS:否 類別:集成電路 (IC) >> 線性 - 模擬乘法器，除法器 系列:- 標(biāo)準(zhǔn)包裝:25 系列:HA 功能:模擬乘法器 位元/級數(shù):四象限 封裝/外殼:16-CDIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:16-CDIP 側(cè)面銅焊 包裝:管件 |
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| AD534JDZ | 功能描述:IC MULTIPLIER PREC TRIM 14-CDIP RoHS:是 類別:集成電路 (IC) >> 線性 - 模擬乘法器，除法器 系列:- 標(biāo)準(zhǔn)包裝:25 系列:HA 功能:模擬乘法器 位元/級數(shù):四象限 封裝/外殼:16-CDIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:16-CDIP 側(cè)面銅焊 包裝:管件 |
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