Data Sheet
AD5310
Rev. B | Page 3 of 16
SPECIFICATIONS
VDD = 2.7 V to 5.5 V; temperature range = 40°C to +105°C RL = 2 k to GND; CL = 500 pF to GND; all specifications TMIN to TMAX unless
otherwise noted
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
Resolution
10
Bits
Relative Accuracy
±4
LSB
Differential Nonlinearity
±0.5
LSB
Zero Code Error
5
40
mV
Full-Scale Error
0.15
1.25
% of FSR
Gain Error
±1.25
% of FSR
Zero Code Error Drift
20
V/°C
Gain Temperature Coefficient
5
ppm of FSR/°C
Output Voltage Range
0
VDD
V
Output Voltage Settling Time
6
8
s
scale to scale change (100 hex to 300 hex)
Slew Rate
1
V/s
Capacitive Load Stability
470
pF
RL = ∞
1000
pF
RL = 2 kΩ
Digital-to-Analog Glitch Impulse
20
nV-s
Digital Feedthrough
0.5
nV-s
DC Output Impedance
1
Ω
Short-Circuit Current
50
mA
VDD = 5 V
20
mA
VDD = 3 V
Power-Up Time
2.5
s
Coming out of power-down mode, VDD = 5 V
5
s
Coming out of power-down mode, VDD = 3 V
Input Current
±1
A
VINL, Input Low Voltage
0.8
V
VDD = 5 V
VINL, Input Low Voltage
0.6
V
VDD = 3 V
VINH, Input High Voltage
2.4
V
VDD = 5 V
VINH, Input High Voltage
2.1
V
VDD = 3 V
Pin Capacitance
3
pF
POWER REQUIREMENTS
VDD
2.7
5.5
V
IDD (Normal Mode)
DAC active and excluding load current
VDD = 4.5 V to 5.5 V
140
250
A
VIH = VDD and VIL = GND
VDD = 2.7 V to 3.6 V
115
200
A
VIH = VDD and VIL = GND
IDD (All Power-Down Modes)
VDD = 4.5 V to 5.5 V
0.2
1
A
VIH = VDD and VIL = GND
VDD = 2.7 V to 3.6 V
0.05
1
A
VIH = VDD and VIL = GND
Power Efficiency
IOUT/IDD
93
%
ILOAD = 2 mA, VDD = 5 V
1
Linearity calculated using a reduced code range of 12 to 1011. Output unloaded.
2
Guaranteed by design and characterization; not production tested.