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參數(shù)資料
| 型號： | AD5300* |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | +2.7 V to +5.5 V. 140 uA. Rail-to-Rail Output 8-Bit DAC in an SOT-23 |
| 中文描述： | 2.7伏至5.5伏140微安。軌到軌輸出8位DAC，采用SOT - 23 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 180K |
CODE
I
1
0.5
–10
50
250
100
150
200
0
–0.5
INL @ 3V
INL @ 5V
T
A
= +25
8
C
Figure 2. Typical INL Plot
TEMPERATURE –
8
C
E
1
0.5
–1
–40
0
120
40
80
0
–0.5
MAX INL
MIN INL
MAX DNL
MIN DNL
V
DD
= +5V
Figure 5. INL Error and DNL Error
vs. Temperature
I
SOURCE/SINK
– mA
V
O
3
2
00
5
15
10
1
DAC LOADED WITH FF HEX
T
A
= +25
8
C
DAC LOADED WITH 00 HEX
Figure 8. Source and Sink Current
Capability with V
DD
= 3 V
CODE
D
0.5
0.4
–0.50
50
250
100
150
200
–0.1
–0.2
–0.3
–0.4
0.3
0.1
0.2
0
T
A
= +25
8
C
DNL @ 5V
DNL @ 3V
Figure 3. Typical DNL Plot
TEMPERATURE –
8
C
3
2
–3
–40
120
0
40
80
0
–1
V
DD
= +5V
E
–2
1
ZS ERROR
FS ERROR
Figure 6. Zero-Scale Error and Full-
Scale Error vs. Temperature
I
SOURCE/SINK
– mA
V
O
5
4
00
5
15
10
3
2
1
DAC LOADED WITH 00 HEX
T
A
= +25
8
C
DAC LOADED WITH FF HEX
Figure 9. Source and Sink Current
Capability with V
DD
= 5 V
CODE
T
1.0
0.5
–1.0
0
50
250
100
150
200
0
–0.5
T
A
= +25
8
C
TUE @ 5V
TUE @ 3V
Figure 4. Typical Total Unadjusted
Error Plot
2500
2000
500
50
1500
1000
0
F
70
90
110
I
DD
–
m
A
130
150
170
190
60
80
100
120
140
160
180
V
DD
= +3V
V
DD
= +5V
Figure 7. I
DD
Histogram with
V
DD
= 3 V and V
DD
= 5 V
CODE
I
D
m
A
500
400
00
50
250
100
150
200
300
200
100
V
DD
= +3V
V
DD
= +5V
Figure 10. Supply Current vs. Code
AD5300–Typical Performance Characteristics
–6–
REV. A
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PDF描述 |
|---|---|
| AD5300BRM | +2.7 V to +5.5 V, 140 uA, Rail-to-Rail Output 8-Bit DAC in an SOT-23 |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
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