參數(shù)資料
型號(hào)： AD5263BRUZ50-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 23/28頁
文件大?。?/td> 0K
描述： IC POT DGTL 50K 256POS 24TSSOP
標(biāo)準(zhǔn)包裝： 1,000
接片： 256
電阻（歐姆）： 50k
電路數(shù)： 4
溫度系數(shù)： 標(biāo)準(zhǔn)值 30 ppm/°C
存儲(chǔ)器類型： 易失
接口： I²C，SPI（芯片選擇，設(shè)備位址）
電源電壓： 2.7 V ~ 5.5 V，5 V ~ 15 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 24-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 24-TSSOP
包裝： 帶卷 (TR)
AD5263
Data Sheet
Rev. F | Page 4 of 28
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
POWER SUPPLIES
Logic Supply8
V
L
2.7
5.5
V
Power Single-Supply Range
V
DD RANGE
V
SS = 0 V
4.5
16.5
V
Power Dual-Supply Range
V
DD/SS RANGE
±4.5
±7.5
V
Logic Supply Current9
I
L
V
L = +5 V
25
60
A
Positive Supply Current
I
DD
V
IH = +5 V or VIL = 0 V
1
A
Negative Supply Current
I
SS
V
SS = –5 V
1
A
Power Dissipation10
P
DISS
V
IH = +5 V or VIL = 0 V, VDD =
+5 V, V
SS = –5 V
0.6
mW
Power Supply Sensitivity
PSS
V
DD = +5 V ± 10%
0.002
0.01
%/%
DYNAMIC CHARACTERISTICS6, 11
Bandwidth (3 dB)
BW
R
AB = 20 k/50 k/200 k
300/150/35
kHz
Total Harmonic Distortion
THD
W
V
A = 1 V rms, VB = 0 V, f = 1 kHz,
R
AB = 20 k
0.05
%
V
W Settling Time
t
S
V
A = 10 V, VB = 0 V, ±1 LSB error
band
2
s
Resistor Noise Voltage
e
N_WB
R
WB = 10 k, f = 1 kHz, RS = 0
9
nV/√Hz
1 Typicals represent average readings at +25°C and V
DD = +5 V, VSS = 5 V.
2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. IW = VDD/R for both VDD = +5 V and
VSS = –5 V.
3 V
AB = VDD, Wiper (VW) = no connect.
4 INL and DNL are measured at V
W with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 The A, B, and W resistor terminals have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode.
8 V
L is limited to VDD or 5.5 V, whichever is less.
9 Worst-case supply current consumed when all logic-input levels set at 2.4 V, standard characteristic of CMOS logic.
10 P
DISS is calculated from IDD × VDD. CMOS logic level inputs result in minimum power dissipation.
11 All dynamic characteristics use V
DD = +5 V, VSS = 5 V, VL = +5 V.
12 Settling time depends on value of V
DD, RL, and CL.
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