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參數(shù)資料
| 型號： | AD5263BRUZ50-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC POT DGTL 50K 256POS 24TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 接片： | 256 |
| 電阻（歐姆）： | 50k |
| 電路數(shù)： | 4 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 30 ppm/°C |
| 存儲器類型： | 易失 |
| 接口： | I²C，SPI（芯片選擇，設(shè)備位址） |
| 電源電壓： | 2.7 V ~ 5.5 V，5 V ~ 15 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 帶卷 (TR) |
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Data Sheet
AD5263
Rev. F | Page 23 of 28
APPLICATIONS INFORMATION
BIPOLAR DC OR AC OPERATION FROM DUAL
SUPPLIES
The AD5263 can be operated from dual supplies, enabling
control of ground referenced ac signals or bipolar operation.
The ac signal, as high as VDD/VSS, can be applied directly across
Terminal A to Terminal B, with the output taken from Terminal W.
03142-
056
GND
SCLK
VDD
AD5263
C
GND
MCSI
SDA
SCL
VDD
VSS
+5.0V
±5V p-p
±2.5V p-p
_
5.0V
D = 0x90
A1
W1
B1
A2
W2
B2
Figure 57. Bipolar Operation from Dual Supplies
GAIN CONTROL COMPENSATION
A digital potentiometer is commonly used in gain control such
as the noninverting gain amplifier shown in Figure 58.
R1
47k
25pF
C1
VI
B
A
R2
VO
U1
W
200k
C2
4.7pF
03142-
057
Figure 58. Typical Noninverting Gain Amplifier
Notice the RDAC B terminal parasitic capacitance is connected to
the op amp noninverting node. It introduces a zero for the 1/βo
term with +20 dB/dec, whereas a typical op amp GBP has
20 dB/dec characteristics. A large R2 and finite C1 can cause
this zero’s frequency to fall well below the crossover frequency.
Thus, the rate of closure becomes 40 dB/dec and the system has
0° phase margin at the crossover frequency. The output may ring or
oscillate if the input is a rectangular pulse or step function.
Similarly, it is also likely to ring when switching between two gain
values, because this is equivalent to a step change at the input.
Depending on the op amp GBP, reducing the feedback resistor
may extend the zero’s frequency far enough to overcome the
problem. A better approach is to include a compensation capacitor
C2 to cancel the effect caused by C1. Optimum compensation
occurs when R1 × C1 = R2 × C2. This is not an option, because
of the variation of R2. As a result, one may use the relationship
described and scale C2 as if R2 is at its maximum value. Doing
so may overcompensate and compromise the performance slightly
when R2 is set at low values. However, it avoids the gain peaking,
ringing, or oscillation in the worst case. For critical applications,
C2 should be found empirically to suit the need. In general, C2
in the range of a few pF to no more than a few tenths of pF is
usually adequate for the compensation.
Similarly, there are W and A terminal capacitances connected to
the output (not shown); fortunately, their effect at this node is less
significant and the compensation can be disregarded in most cases.
PROGRAMMABLE VOLTAGE REFERENCE
For voltage divider mode operation (Figure 59), it is common to
buffer the output of the digital potentiometer unless the load is
much larger than RWB. Not only does the buffer serve the purpose
of impedance conversion, but it also allows a heavier load to be
driven.
03142-
058
U1
VIN
W
B
A
GND
VO
AD8601
1
A1
5V
VOUT
3
5V
AD5263
AD1582
Figure 59. Programmable Voltage Reference
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