參數(shù)資料
型號: AD5100
廠商: Analog Devices, Inc.
英文描述: System-Management IC with Programmable Quad Voltage Monitoring and Supervisory Functions
中文描述: 系統(tǒng)管理IC與可編程四路電壓監(jiān)測和監(jiān)督職能
文件頁數(shù): 23/32頁
文件大小: 495K
代理商: AD5100
Preliminary Technical Data
AD5100
Rev. PrJ | Page 23 of 32
B
W
[2:0] – 3 bits used to program RESET Hold time
[7:3] – Reserved
(200 mS)
0x0
C
R/W
Y
Watchdog Timeout
[2:0] – 3 bits used to program Watchdog timeout time
[7:3] – Reserved
0x00
(1500 mS)
0x0
D
R/
W
Y
RESET Configuration
[0] – 0 - RESET is active when SHDN is active
1 - RESET is not active when SHDN is active
[1] – Reserved
[2] – 0 - Enable V
4MON
over threshold to cause RESET
1 - Prevent V
4MON
over threshold to cause RESET (For V
4OUT
Application)
[3] – 0 - Prevent floating WDI to cause RESET
1 - Enable floating WDI to cause RESET
[7:4] – Reserved
0x00
0x0E
R/
W
Y
SHDN Rail Voltage Configuration
[2:0] – Reserved
[3] – 0 - SHDN rail = V
1MON
1 - SHDN rail = Vreg
[7:4] – Reserved
0x00
0x0F
R/
W
Y
Watchdog Mode
[2:0] – Reserved
[3] – 0 – Standard Mode
1 – Advanced Mode
[7:4] – Reserved
0x00
0x15
R/
W
Y
Program Lock Fuse (Inhibit Further Programming)
[2:0] – Reserved
[3] – 0 – Fuse Programming allowed
1 – Fuse Programming Disabled
[7:4] – Reserved
0x00
0x16
R/
W
N
Special Functions 1
[0] – 0 – OTP Enable A Inactive
1 – OTP Enable A Active
[1] – 0 - OTP Enable B Inactive
1 - OTP Enable B Active
[2] – 0 – Software assertion of SHDN Inactive
0x00
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