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參數(shù)資料
| 型號： | AD1959YRSRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | PLL/Multibit DAC |
| 中文描述： | SERIAL INPUT LOADING, DAC WITH PROGRAMMABLE PLL, PDSO28 |
| 封裝： | PLASTIC, SSOP-28 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 107K |
| 代理商： | AD1959YRSRL |
REV. 0
AD1959
–5–
PIN FUNCTION DESCRIPTIONS
Pin
Input/Output
Mnemonic
Description
1
I
CCLK
Control Clock Input for Control Data. Control input data must be valid on
the rising edge of CCLK. CCLK may be continuous or gated.
Latch Input for Control Data.
Reset. The AD1959 is placed in a reset mode when this pin is held LO.
The serial control port registers are reset to their default values. Set HI for
normal operation.
Left/Right Clock Input for Input Data. Must run continuously.
Bit Clock Input for Input Data. Need not run continuously; may be gated
or used in a burst fashion.
Serial input, MSB first, containing two channels of 16/20/24 bits of two’s-
complement data per channel.
Digital Power Supply Connect to Digital 5 V Supply.
Digital Ground.
33.8688 MHz Clock Output.
27 MHz Master Clock Output/256 f
S
DAC Clock Input.
27 MHz Crystal Oscillator Output.
27 MHz Crystal Oscillator/External Clock Input.
256/384 f
S
Output.
512 f
S
/22.5792 MHz Output.
PLL Power Supply. Connect to PLL 5 V Supply.
PLL Ground.
PLL0 Loop Filter.
PLL1 Loop Filter.
Analog Ground.
Right Channel Positive Line Level Analog Output.
Voltage Reference Filter Capacitor Connection. Bypass and decouple the
voltage reference with parallel 10
μ
F and 0.1
μ
F capacitors to AGND.
Analog Ground.
Left Channel Line Level Analog Output.
Analog Power Supply. Connect to Analog 5 V Supply.
Filter Capacitor Connection, Connect 10
μ
F Capacitor to AGND.
Zero Flag Output. This pin goes HI when both channels have zero signal
input for more than 1024 L/R Clock Cycles.
Mute. Assert HI to Mute Both Stereo Analog Outputs. Deassert LO for
normal operation.
Serial control input, MSB first, containing 16 bits of unsigned data
per channel.
2
3
I
I
CLATCH
RESET
4
5
I
I
LRCLK
BCLK
6
I
SDATA
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
I
I
O
I/O
O
I
O
O
DVDD
DGND
SCLK0
MCLK
XOUT
XIN
SCLK1
SCLK2
PVDD
PGND
LF0
LF1
AGND0
OUTR
FILTR
O
O
22
23
24
25
26
I
O
AGND1
OUTL
AVDD
FILTB
ZERO
O
27
I
MUTE
28
I
CDATA
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