- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄10218 > AD1941YSTZRL (Analog Devices Inc)IC DSP AUDIO 16CHAN 28BIT 48LQFP PDF資料下載
參數(shù)資料
| 型號： | AD1941YSTZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP AUDIO 16CHAN 28BIT 48LQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 系列： | SigmaDSP® |
| 類型： | 音頻處理器 |
| 應(yīng)用： | 車載系統(tǒng)，家庭影院，電視 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
第1頁第2頁當(dāng)前第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁
AD1940/AD1941
Rev. B | Page 11 of
36
FEATURES
The core of the AD1940/AD1941 is a 28-bit DSP (56-bit, double
precision) optimized for audio processing. The parts’ program
RAM can be loaded with a custom program after power-up.
Signal processing parameters are stored in a 1024 location
parameter RAM, which is initialized on power-up by an
internal boot ROM. New values are written to the parameter
RAM using the control port. The values stored in the parameter
RAM control individual signal processing blocks, such as IIR
equali-zation filters, dynamics processors, audio delays, and
mixer levels. A safeload feature allows parameters to be
transparently updated without causing clicks on the output
signals.
The target/slew RAM contains 64 locations and can be used as
channel volume controls or for other parameter updates. These
RAM locations take a target value for a given parameter and
ramp the current parameter value to the new value using a
specified time constant and one of a selection of linear or
logarithmic curves.
The AD1940/AD1941 contain eight independent data capture
circuits that can be programmed to tap the signal flow of the
processor at any point in the DSP algorithm flow. Six of these
captured signals can be accessed by reading from the data
capture registers through the control port. The remaining two
data capture registers can be used to send any internal captured
signal to a stereo digital output signal on Pin SDATA_OUT7 for
driving external DACs or digital analyzers.
The AD1940/AD1941 have a sophisticated control port that
supports complete read/write capability of all memory
locations. Five control registers (Core, RAM configuration,
Serial Output 0 to 7, Serial Output 8 to 15, and serial input) are
provided to offer complete control of the chip’s configuration
and serial modes. Handshaking is included for ease of memory
uploads/downloads. The AD1940 is SPI-controlled and the
AD1941 is controlled by an I2C bus.
The AD1940/AD1941 have very flexible serial data
input/output ports that allow glueless interconnection to a
variety of ADCs, DACs, general-purpose DSPs, S/PDIF
receivers and trans-mitters, and sample rate converters. The
AD1940/AD1941 can be configured in I2S, left-justified, right-
justified, or TDM serial port-compatible modes. It can support
16, 20, and 24 bits in all modes. The AD1940/AD1941 accepts
serial audio data in MSB first and twos complement format.
A master clock phase-locked loop (PLL) allows the AD1940/
AD1941 to be clocked from a variety of different clock speeds.
The PLL can accept inputs of 64 × fS, 256 × fS, 384 × fS, or 512 ×
fS to generate the core’s internal master clock.
The AD1940/AD1941 operate from a single 2.5 V power supply.
An on-board voltage regulator can be used to operate the chip
with 3.3 V or 5 V supplies. They are fabricated on a single
monolithic integrated circuit and are housed in 48-lead
LQFP packages for operation over the –40°C to +105°C
temperature range.
04607-0-003
28
× 28
DSP CORE
DATA FORMAT:
5.23 (SINGLE PRECISION)
10.46 (DOUBLE PRECISION)
VOLTAGE REGULATOR
MEMORY CONTROLLERS
CONTROL
REGISITER
TRAP REG.
SAFELOAD
REGISTER
SERIAL
CONTROL
PORT
MCLK
PLL
DATA MEMORY
6k
× 28
TARGET/SLEW
RAM
64
× 28
SERIAL
DATA/TDM
INPUT
GROUP
PLL MODE
SELECT
MASTER
CLOCK
INPUT
CONTROL PORT
I/O GROUP
RESETB
PROGRAM
RAM
1536
× 40
BOOT
ROM
BOOT
ROM
PARAMETER
RAM
1024
× 28
COEFFICIENT
ROM
512
× 28
2
4
2
SERIAL DATA/
TDM OUTPUT
GROUP
REGULATOR
GROUP
ADDRESS SELECT
Figure 9. Block Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD1940YSTZRL | IC DSP AUDIO 16CH/28BIT 48-LQFP |
| SP3243EUEA-L/TR | IC TXRX RS232 INTELLIGENT 28SSOP |
| VE-21J-IU-F2 | CONVERTER MOD DC/DC 36V 200W |
| ADAU1446YSTZ-3A-RL | IC SIGMADSP 175MHZ 100LQFP |
| SP3243EUCA-L/TR | IC TXRX RS232 INTELLIGENT 28SSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1953 | 制造商:AD 制造商全稱:Analog Devices 功能描述:SigmaDSP⑩ 3-Channel, 26-Bit Signal Processing DAC |
| AD1953YST | 制造商:Analog Devices 功能描述:DAC 3-CH Delta-Sigma 24-bit 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:3 CHANNEL 24 BIT SIGNAL-PROCESSING DAC - Tape and Reel 制造商:Analog Devices 功能描述:IC 24BIT DAC SMD 1953 LQFP48 |
| AD1953YSTRL | 制造商:Analog Devices 功能描述:DAC 3-CH Delta-Sigma 24-bit 48-Pin LQFP T/R |
| AD1953YSTRL7 | 制造商:Analog Devices 功能描述:DAC 3-CH Delta-Sigma 24-bit 48-Pin LQFP T/R 制造商:Rochester Electronics LLC 功能描述:3 CHANNEL 24 BIT SIGNAL-PROCESSING DAC - Tape and Reel |
| AD1953YSTZ | 功能描述:IC DSP DAC AUDIO3CH/26BIT 48LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:SigmaDSP® 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。