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參數資料
| 型號： | AD1941YSTZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 14/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP AUDIO 16CHAN 28BIT 48LQFP |
| 標準包裝： | 2,000 |
| 系列： | SigmaDSP® |
| 類型： | 音頻處理器 |
| 應用： | 車載系統(tǒng)，家庭影院，電視 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應商設備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
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AD1940/AD1941
Rev. B | Page 21 of
36
The four ramping curve types are
Linear—Value slews to target using a fixed step size.
Constant dB—Value slews to target using the current value
to calculate the step size. The resulting curve has a
constant rise and decay when measured in dB.
RC type—Value slews to target using the difference
between target and current values to calculate the step size,
producing a simple RC type curve for rising and falling.
Constant Time—Value slews to the target in a fixed
number of steps in a linear fashion. The control port mute
has no affect on this type.
Table 21. Target/Slew RAM Ramp Type Settings
Setting
Ramp Type
00
Linear
01
Constant dB
10
RC type
11
Constant time
The following sections detail how the control port writes to
the target/slew RAM to control the time constant and ramp
type parameters.
Ramp Types 1 to 3: Linear, Constant dB, RC Type (34-Bit
Write)
The target word for the first three ramp types is broken up into
three parts. The 34-bit command is written with six leading 0s
to extend the data write to five bytes. The parts of the target
RAM write are the following:
Ramp Type (2 bits)
Time Constant (4 bits)
0000 = Fastest
1111 = Slowest
Data (28 Bits): 5.23 Format
Ramp Type 4—Constant Time (34-Bit Write)
The target word for the constant time ramp type is written in
five parts, with the 34-bit command again written with six
leading zeros to extend the data write to five bytes. The parts of
the constant time target RAM write are the following:
Ramp Type (2 bits).
Update Step (1 bit). Set to 1 when new target is loaded to
trigger step value update. Value is automatically reset after
the step value is updated.
Number of Steps (3 bits). The number of steps that it takes
to slew to the target value is set by these three bits, with the
number of steps equal to 23-bit setting + 6.
000 = 64
001 = 128
010 = 256
011 = 512
100 = 1024
101 = 2048
110 = 4096
111 = 8196
Data (16 bits). 2.14 format.
Reserved (12 bits). When writing to the RAM, these bits
should all be set to 0.
Target and Slew RAM Initialization
On reset, the target/slew RAM initializes to preset values. The
target RAM initializes to a linear ramp type with a time
constant of 5 and the data set to 1.0. The slew RAM initializes to
a value of 1.0. These defaults give a full-scale (1.0 to 0.0) ramp
time of 21.3 ms.
Linear Update Math
Linear math is the addition or subtraction of a constant value
(step). The equation to describe this step size is
()
20
10
13
5
2
×
=
tconst
step
The result of the equation is normalized to a 5.23 data format.
This gives a time constant range from 6.75 ms to 213.4 ms
(–60 dB relative to 0 dB full scale). An example of this kind of
update is shown in Figure 15 and Figure 16. All slew RAM
figure examples, except the half-scale constant time ramp plot,
show an increasing or decreasing ramp between –80 dB and
0 dB (full scale). All figures except the constant time plots
(Figure 19 and Figure 21) use a time constant of 0x7 (0x0 being
the fastest and 0xF being the slowest).
TIME (ms)
OUTPUT
LEVEL
(V)
1
0.4
0.6
0.8
0.2
0
–0.4
–0.2
–1
–0.8
–0.6
010
20
30
04607-0-017
Figure 15. Slew RAM—Linear Update Increasing Ramp
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| AD1953YSTZ | 功能描述:IC DSP DAC AUDIO3CH/26BIT 48LQFP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 數模轉換器 系列:SigmaDSP® 產品培訓模塊:Data Converter Fundamentals DAC Architectures 標準包裝:750 系列:- 設置時間:7µs 位數:16 數據接口:并聯 轉換器數目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應商設備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
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