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參數(shù)資料
| 型號： | AD1941YSTZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/36頁 |
| 文件大小： | 0K |
| 描述： | IC DSP AUDIO 16CHAN 28BIT 48LQFP |
| 標準包裝： | 2,000 |
| 系列： | SigmaDSP® |
| 類型： | 音頻處理器 |
| 應用： | 車載系統(tǒng)，家庭影院，電視 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應商設備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
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AD1940/AD1941
Rev. B | Page 19 of
36
RAMS AND REGISTERS
Table 17. Control Port Addresses
SPI/ I2C Subaddress
Register Name
Read/Write Word Length
0–1023 (0x0000–0x03FF)
Parameter RAM
Write: 4 bytes, read: 4 bytes
1024–2559 (0x0400–0x09FF)
Program RAM
Write: 5 bytes, read: 5 bytes
2560–2623 (0x0A00–0x0A3F)
Target/Slew RAM
Write: 5 bytes, read: n/a
2624–2628 (0x0A40–0x0A44)
Parameter RAM Data Safeload Registers 0–4
Write: 5 bytes, read: n/a
2629–2633 (0x0A45–0x0A49)
Parameter RAM Indirect Address Safeload Registers 0–4
Write: 2 bytes, read: n/a
2634–2639 (0x0A4A–0x0A4F)
Data Capture Registers 0–5 (Control Port Readback)
Write: 2 bytes, read: 3 bytes
2640–2641 (0x0A50–0x0A51)
Data Capture Registers (Digital Output)
Write: 2 bytes, read: n/a
2642 (0x0A52)
DSP Core Control Register
Write: 2 bytes, read: 2 bytes
2643 (0x0A53)
RAM Configuration Register
Write: 1 byte, read: 1 byte
2644 (0x0A54)
Serial Output Control Register 1 (Channels 0–7)
Write: 2 bytes, read: 2 bytes
2645 (0x0A55)
Serial Output Control Register 2 (Channels 8–15)
Write: 2 bytes, read: 2 bytes
2646 (0x0A56)
Serial Input Control Register
Write: 1 byte, read: 1 byte
Table 18. RAM Read/Write Modes
Memory
Size
Subaddress
Range
Read
Write
Burst Mode
Available
Write Modes
Parameter RAM
1024 × 28
0–1023
(0x0000–0x03FF)
Yes
Direct write1 or safeload write
Program RAM
1536 × 40
1024–2559
(0x0400–0x09FF)
Yes
Direct write1
Target/Slew RAM
64 × 34
2560–2623
(0x0A00–0x0A3F)
No
Yes (via
safeload)
Yes2
Safeload write
1 DSP core should be shut down first to avoid clicks/pops.
2 The target/slew RAMs need to be written through the safeload registers. Safeload writes may be done in either single write mode or burst mode.
CONTROL PORT ADDRESSING
Table 17 shows the addressing of the AD1940/AD1941’s RAM
and register spaces. The address space encompasses a set of
registers and three RAMs: one each for holding signal
processing parameters, holding the program instructions, and
ramping parameter values. The program and parameter RAMs
are initialized on power-up from on-board boot ROMs.
Table 18 shows the sizes and available writing modes of the
PARAMETER RAM CONTENTS
The parameter RAM is 28 bits wide and occupies Addresses 0 to
1023. The parameter RAM is initialized to all 0s on power-up.
The data format of the parameter RAM is twos complement
5.23. This means that the coefficients may range from +16.0
(minus 1 LSB) to –16.0, with 1.0 represented by the binary word
0000 1000 0000 0000 0000 0000 0000.
Options for Parameter Updates
The parameter RAM can be written and read using one of the
two following methods.
1.
Direct Read/Write
. This method allows direct access to
the program and parameter RAMs. This mode of operation
is normally used during a complete new load of the RAMs,
using burst mode addressing. The clear register bit in the
core control register should be set to 0 using this mode to
avoid any clicks or pops in the outputs. Note that it is also
possible to use this mode during live program execution,
but since there is no handshaking between the core and the
control port, the parameter RAM is unavailable to the DSP
core during control writes, resulting in clicks and pops in
the audio stream.
2.
Safeload Write.
Up to five safeload registers can be loaded
with parameter RAM address/data. The data is then
transferred to the requested address when the RAM is not
busy. This method can be used for dynamic updates while
live program material is playing through the AD1940/
AD1941. For example, a complete update of one biquad
section can occur in one audio frame, while the RAM is
not busy. This method is not available for writing to the
program RAM or control registers.
The following sections discuss these two options in more detail.
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