參數(shù)資料
型號: AD1895AYRSRL
廠商: ANALOG DEVICES INC
元件分類: 消費家電
英文描述: 192 kHz Stereo Asynchronous Sample Rate Converter
中文描述: SPECIALTY CONSUMER CIRCUIT, PDSO28
封裝: PLASTIC, MO-150AH, SSOP-28
文件頁數(shù): 3/24頁
文件大小: 816K
代理商: AD1895AYRSRL
REV. A
–3–
AD1895
DIGITAL TIMING (–40 C < T
A
< +105 C, VDD_CORE = 3.3 V 5%, VDD_IO = 5.0 V 10%)
Parameter
1
Min
Max
Unit
t
MCLKI
f
MCLK
t
MPWH
t
MPWL
Input Serial Port Timing
t
LRIS
t
SIH
t
SIL
t
DIS
t
DIH
Output Serial Port Timing
t
TDMS
t
TDMH
t
DOPD
t
DOH
t
LROS
t
LROH
t
SOH
t
SOL
t
RSTL
MCLK_I Period
MCLK_I Frequency
MCLK_I Pulsewidth High
MCLK_I Pulsewidth Low
33.3
ns
MHz
ns
ns
30.0
2, 3
8
12
LRCLK_I Setup to SCLK_I
SCLK_I Pulsewidth High
SCLK_I Pulsewidth Low
SDATA_I Setup to SCLK_I Rising Edge
SDATA_I Hold from SCLK_I Rising Edge
8
8
8
8
3
ns
ns
ns
ns
ns
TDM_IN Setup to SCLK_O Falling Edge
TDM_IN Hold from SCLK_O Falling Edge
SDATA_O Propagation Delay from SCLK_O, LRCLK_O
SDATA_O Hold from SCLK_O
LRCLK_O Setup to SCLK_O (TDM Mode Only)
LRCLK_O Hold from SCLK_O (TDM Mode Only)
SCLK_O Pulsewidth High
SCLK_O Pulsewidth Low
RESET Pulsewidth LO
3
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
3
5
3
10
5
200
NOTES
1
Refer to Timing Diagram Section.
2
The maximum possible sample rate is:
FS
=
f
/138.
3
f
MCLK
of up to 34 MHz is possible under the following conditions: 0
°
C < T
A
< 70
°
C, 45/55 or better MCLK_I duty cycle.
Specifications subject to change without notice.
TIMING DIAGRAMS
t
LRIS
t
SIH
t
DIS
t
SIL
t
DIH
t
LROS
t
SOH
t
DOPD
t
SOL
t
DOH
t
LROH
t
TDMS
t
TDMH
LRCLK_I
SCLK I
SDATA I
LRCLK O
SCLK O
SDATA O
LRCLK O
SCLK O
TDM IN
Figure 1. Input and Output Serial Port Timing (SCLK I/O,
LRCLK I/O, SDATA I/O, TDM_IN)
t
RSTL
MCLK I
RESET
Figure 2.
RESET
Timing
t
MPWH
t
MPWL
Figure 3. MCLK_I Timing
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