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參數(shù)資料
| 型號： | AD1895AYRSRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | 192 kHz Stereo Asynchronous Sample Rate Converter |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO28 |
| 封裝： | PLASTIC, MO-150AH, SSOP-28 |
| 文件頁數(shù)： | 19/24頁 |
| 文件大小： | 816K |
| 代理商： | AD1895AYRSRL |
REV. A
AD1895
–19–
OPERATING FEATURES
RESET
and Power Down
When
RESET
is asserted low, the AD1895 will turn off the
master clock input to the AD1895, MCLK_I, initialize all of its
internal registers to their default values, and three-state all of the
I/O pins. While
RESET
is active low, the AD1895 is consuming
minimum power. For the lowest possible power consumption
while
RESET
is active low, all of the input pins to the AD1895
should be static.
When
RESET
is deasserted, the AD1895 begins its initialization
routine where all locations in the FIFO are initialized to zero,
MUTE_OUT is asserted high, and any I/O pins configured as
outputs are enabled. The mute control counter, which controls
the soft mute attenuation of the input samples, is initialized to
maximum attenuation, –127 dB (see Mute Control section).
When asserting
RESET
and deasserting
RESET
, the
RESET
should be held low for a minimum of 5 MCLK_I cycles. During
power-up the
RESET
should be held low until the power sup-
plies have stabilized.
Power Supply and Voltage Reference
The AD1895 is designed for three-volt operation with five-volt
input tolerance on the input pins. VDD_CORE is the three-volt
supply that is used to power the core logic of the AD1895 and
to drive the output pins. VDD_IO is used to set the input volt-
age tolerance of the input pins. In order for the input pins to be
five-volt input tolerant, VDD_IO must be connected to a five-
volt supply. If the input pins do not have to be five-volt input
tolerant, then VDD_IO can be connected to VDD_CORE.
VDD_IO should never be less than VDD_CORE. VDD_CORE
and VDD_IO should be bypassed with 100 nF ceramic chip
capacitors, as close to the pins as possible, to minimize power
supply and ground bounce caused by inductance in the traces. A
bulk aluminium electrolytic capacitor of 47
μ
F should also be
provided on the same PC board as the AD1895.
Digital Filter Group Delay
The filter group delay is given by the equation:
GD
f
f
for f
f
GD
f
f
f
f
for f
f
S
IN
S
IN
S OUT
_
S
IN
S
IN
S
IN
S
IN
S OUT
_
S OUT
_
S
IN
=
+
>
=
+
×
<
16
32
16
32
_
_
_
_
_
_
_
seconds
seconds
Mute Control
When the MUTE_IN pin is asserted high, the MUTE_IN control
will perform a soft mute by linearly decreasing the input data
to the AD1895 FIFO to almost zero,
–
127 dB attenuation. When
MUTE_IN is deasserted low, the MUTE_IN control will linearly
decrease the attenuation of the input data to 0 dB. A 12-bit
counter, clocked by LRCLK_I is used to control the mute attenu-
ation. Therefore, the time it will take from the assertion of
MUTE_IN to
–
127 dB full mute attenuation is 4096/LRCLK_I
seconds. Likewise, the time it will take to reach 0 dB mute
attenuation from the deassertion of MUTE_IN is 4096/
LRCLK_I seconds.
Upon
RESET
, or a change in the sample rate between LRCLK_I
and LRCLK_O, the MUTE_OUT pin will be asserted high. The
MUTE_OUT pin will remain asserted high until the digital
servo loop
’
s internal fast settling mode has completed. When
the digital servo loop has switched to slow settling mode, the
MUTE_OUT pin will deassert. While MUTE_OUT is asserted,
the MUTE_IN pin should be asserted as well to prevent any
major distortion in the audio output samples.
Master Clock
A digital clock connected to the MCLK_I pin or a fundamental or
third overtone crystal connected between MCLK_I and MCLK_O
can be used to generate the master clock, MCLK_I. The MCLK_I
pin can be five-volt input-tolerant just like any of the other
AD1895 input pins. A fundamental mode crystal can be inserted
between MCLK_I and MCLK_O for master clock frequency
generation up to 27 MHz. For master clock frequency genera-
tion with a crystal beyond 27 MHz it is recommended that the
user use a third overtone crystal and to add an LC filter at the
output of MCLK_O to filter out the fundamental, do not notch
filter the fundamental. Please refer to your quartz crystal supplier
for values for external capacitors and inductor components.
AD1895
MCLK_I
MCLK_O
C1
C2
R = 45
Figure 9a. Fundamental-Mode Circuit Configuration
AD1895
MCLK_I
MCLK_O
C1
C2
R = 45
1nF
L1
Figure 9b. Third-Overtone Circuit Configuration
There are, of course, maximum and minimum operating fre-
quencies for the AD1895 master clock. The maximum master
clock frequency at which the AD1895 is guaranteed to operate is
30 MHz. 30 MHz is more than sufficient to sample rate convert
sampling frequencies of 192 kHz + 12%. The minimum required
frequency for the master clock generation for the AD1895 depends
upon the input and output sample rates. The master clock has
to be at least 138 times greater than the maximum input or
output sample rate.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1895AYRSZ | 功能描述:IC CONV SAMPLE RATE ASYNC 28SSOP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:- 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
| AD1895AYRSZRL | 功能描述:IC SAMP-RATEHP/CONV 24BIT 28SSOP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:- 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
| AD1895YRS | 制造商:Rochester Electronics LLC 功能描述:192KHZ 8:1 STEREO ASYNC S - Bulk |
| AD1895YRSRL | 制造商:Rochester Electronics LLC 功能描述:192KHZ 8:1 STEREO ASYNC S - Bulk |
| AD1896 | 制造商:AD 制造商全稱:Analog Devices 功能描述:192 kHz Stereo Asynchronous Sample Rate Converter |
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