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參數(shù)資料
| 型號(hào)： | AD1895AYRSRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | 192 kHz Stereo Asynchronous Sample Rate Converter |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO28 |
| 封裝： | PLASTIC, MO-150AH, SSOP-28 |
| 文件頁(yè)數(shù)： | 20/24頁(yè) |
| 文件大小： | 816K |
| 代理商： | AD1895AYRSRL |
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REV. A
AD1895
–20–
Serial Data Ports—Data Format
The serial data input port mode is set by the logic levels on the
SMODE_IN_0/1/2 pins. The serial data input port modes avail-
able are Left Justified, I
2
S and Right Justified (RJ), 16, 18, 20,
or 24 bits as defined in Table I.
Table I. Serial Data Input Port Mode
SMODE_IN_[0:2]
Interface Format
2
1
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Left Justified
I
2
S
Undefined
Undefined
Right Justified, 16 Bits
Right Justified, 18 Bits
Right Justified, 20 Bits
Right Justified, 24 Bits
The serial data output port mode is set by the logic levels on the
SMODE_OUT_0/1 and WLNGTH_OUT_0/1 pins. The serial
mode can be changed to Left Justified, I
2
S, Right Justified or
TDM as defined in the following table. The output word width
can be set by using the WLNGTH_OUT_0/1 pins as shown in
the Word Width table. When the output word width is less than
24 bits, dither is added to the truncated bits. The Right Justified
serial data out mode assumes 64 SCLK_O cycles per frame,
divided evenly for left and right.
Table II. Serial Data Output Port Mode
SMODE_OUT_[0:2]
Interface Format
1
0
0
0
1
1
0
1
0
1
Left Justified (LJ)
I
2
S
TDM Mode
Right Justified (RJ)
Table III. Word Width
WLNGTH_OUT_[0:1]
Word Width
1
0
0
0
1
1
0
1
0
1
24 Bits
20 Bits
18 Bits
16 Bits
The following timing diagrams show the serial mode formats.
MSB
1/f
s
TDM MODE
–
16 TO 24 BITS PER CHANNEL
LEFT CHANNEL
RIGHT CHANNEL
LEFT CHANNEL
LEFT CHANNEL
RIGHT CHANNEL
RIGHT CHANNEL
MSB
LSB
LSB
LSB
LSB
LSB
LSB
MSB
LSB
MSB
LSB
LRCLK
SCLK
SDATA
LRCLK
SCLK
SDATA
LRCLK
SCLK
SDATA
LRCLK
SCLK
SDATA
NOTES:
1. LRCLK NORMALLYOPERATES AT ASSOCIATIVE INPUT OR OUTPUT SAMPLE FREQUENCY (f
s
)
2. SCLK FREQUENCY IS NORMALLY 64 LRCLK EXCEPT FOR TDM MODE WHICH IS N
64
f
s
,
WHERE N = NUMBER OF STEREO CHANNELS IN THE TDM CHAIN, IN MASTER MODE N = 4
MSB
MSB
MSB
MSB
I
2
S MODE
–
16 TO 24 BITS PER CHANNEL
RIGHT JUSTIFIED MODE
–
SELECT NUMBER OF BITS PER CHANNEL
LEFT JUSTIFIED MODE
–
16 TO 24 BITS PER CHANNEL
Figure 10. Input/Output Serial Data Formats
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1895AYRSZ | 功能描述:IC CONV SAMPLE RATE ASYNC 28SSOP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:- 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
| AD1895AYRSZRL | 功能描述:IC SAMP-RATEHP/CONV 24BIT 28SSOP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:- 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
| AD1895YRS | 制造商:Rochester Electronics LLC 功能描述:192KHZ 8:1 STEREO ASYNC S - Bulk |
| AD1895YRSRL | 制造商:Rochester Electronics LLC 功能描述:192KHZ 8:1 STEREO ASYNC S - Bulk |
| AD1896 | 制造商:AD 制造商全稱:Analog Devices 功能描述:192 kHz Stereo Asynchronous Sample Rate Converter |
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