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參數(shù)資料
| 型號： | AD1895 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 3 V/5 V Digital Audio Receiver,External APLL(數(shù)字音頻接收器) |
| 中文描述： | 3伏/ 5 V數(shù)字音頻接收器，外部美集（數(shù)字音頻接收器） |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 130K |
| 代理商： | AD1895 |
AD1895
REV. 0
–6–
Clock Output Signals
Pin Name SSOP
I/O
Description
CLK 256
12
O
CLK 256 is an output clock at a frequency of 256 times the recovered sample frequency (i.e.,
LRCLK ). Useful for downstream digital audio devices such as DACs, sample rate converters, DSPs
and digital audio transmitters.
E rror Output Signals
Pin Name SSOP
I/O
Description
ERROR
18
O
T he ERROR pin is HI when there is no biphase-mark signal present, or when the frequency of the
ASCLK input (Pin 6) frequency is too low for the AD1895 to function properly. T he ERROR bit can be
clocked using the SFCLK signal (Pin 13). NOT E: When no biphase-mark signal is present or the
ASCLK input frequency is too low, the DLRCLK (Pin 24) signal that the external PLL locks to is
changed to a divided-down version of the PLL clock. T his divide ratio is set such that the PLL should
“park” at the highest frequency possible. T his is important to prevent “l(fā)atch-up” where the clock input
signal frequency is too low to be able to decode the left/right clock from the biphase-mark stream, which
makes the PLL go to an even lower frequency, and then the system is “stuck” and unable to recover.
PARIT Y is the computed parity status from the biphase-mark stream. Even parity is computed and
compared against the incoming parity bit, which occurs on each subframe. T he parity output (error
= HI or no error = LO) is held for the entire subframe, until the next parity bit arrives. T his output
is not affected by the subframe select pin (CSLR, Pin 5); the parity check is done on each subframe.
T he PARIT Y bit can be clocked using the SFCLK signal (Pin 13).
PARIT Y
17
O
Subframe Status Output Signals
Pin Name SSOP
I/O
Description
VBIT
14
O
VBIT is the validity bit from the biphase-mark stream, fed out serially, valid on the rising edge of the
SFCLK signal (Pin 13). VBIT = 0 indicates that the current audio sample is suitable for further pro-
cessing (i.e., valid). VBIT = 1 indicates that the current audio sample is not suitable for further pro-
cessing (i.e., not valid). Not affected by the subframe select pin (CSLR, Pin 5). Changes at the
subframe rate (two times the sample rate).
UBIT is the user bit from the biphase-mark stream, fed out serially, valid on the rising edge of the
SFCLK signal (Pin 13). Not affected by the subframe select pin (CSLR, Pin 5). Changes at the
subframe rate (two times the sample rate).
CSBIT is the channel status bit from the biphase-mark stream, fed out serially, valid on the rising
edge of the SFCLK signal (Pin 13). Not affected by the subframe select pin (CSLR, Pin 5).
Changes at the subframe rate (two times the sample rate).
T his clock is used to clock the VBIT , UBIT , CSBIT , PARIT Y and ERROR output status signals.
Active HI (rising edge active), see Figure 21 for timing. It is a pulse at the subframe rate (two times
the sample rate).
UBIT
16
O
CSBIT
15
O
SFCLK
13
O
Reset
Pin Name SSOP
I/O
Description
RESET
9
I
RESET is an active HI signal which, when asserted, clears all on-chip registers on the AD1895 to
their default state.
Power Supply Connections
Pin Name SSOP
I/O
Description
DV
DD
DGND
22
8
Digital Supply. +3 V to +5 V nominal supply voltage.
Digital Ground. +0 V nominal supply connection.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD1895AYRS | 制造商:Analog Devices 功能描述:Sample Rate Converter 28-Pin SSOP 制造商:Rochester Electronics LLC 功能描述:192KHZ 8:1 STEREO ASYNC SAMPLE RATE CONV - Bulk 制造商:Analog Devices 功能描述:IC STEREO ASR CONVERTER |
| AD1895AYRSRL | 制造商:Analog Devices 功能描述:Sample Rate Converter 28-Pin SSOP T/R |
| AD1895AYRSZ | 功能描述:IC CONV SAMPLE RATE ASYNC 28SSOP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:- 其它有關文件:STA321 View All Specifications 標準包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應商設備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
| AD1895AYRSZRL | 功能描述:IC SAMP-RATEHP/CONV 24BIT 28SSOP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:- 其它有關文件:STA321 View All Specifications 標準包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應商設備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
| AD1895YRS | 制造商:Rochester Electronics LLC 功能描述:192KHZ 8:1 STEREO ASYNC S - Bulk |
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