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參數(shù)資料
| 型號(hào)： | AD1895 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 3 V/5 V Digital Audio Receiver,External APLL(數(shù)字音頻接收器) |
| 中文描述： | 3伏/ 5 V數(shù)字音頻接收器，外部美集（數(shù)字音頻接收器） |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 130K |
| 代理商： | AD1895 |
AD1895
REV. 0
–5–
T able II summaries the function of the CA through CE pins, depending on the operating mode
(professional or consumer).
T able II. Decoded Channel Status Output Functions
Pin
C onsumer
CA
0 = Audio, 1 = Non-Audio
CB
0 = Copy Permitted, 1 = Copy Inhibited
CC
0 = Pre-emphasis, 1 = No Pre-emphasis
CD
0 = Original, 1 = Copy
CE
0 = Ignorant Category, 1 = Not Ignorant
Professional
0 = Audio, 1 = Non-Audio
Pre-emphasis Encoding
Pre-emphasis Encoding
Inverse of Channel Status Bit 9
0 = C.S. CRC Error, 1 = No C.S. CRC Error
CON/
PRO
27
O
CON/
PRO
is defined as the inverse of channel status bit 0, byte 0 (C0, pro/consumer). CON/
PRO
= 0
indicates professional mode. CON/
PRO
= 1 indicates consumer mode. T he state of this pin inter-
nally determines the consumer/pro mode of the CA, CB, CC, CD and CE pins.
Channel Status Clock. Active HI (rising edge active). Outputs a pulse every 192 frames, at the start
of the channel status block. Use this clock to latch the CA through CE and CON/
PRO
output chan-
nel status signals. See Figure 22 for timing.
CSCLK
26
O
Channel Status Input Control Signal
Pin Name SSOP
I/O
Description
CSLR
5
I
T his input determines whether CA through CE and CON/
PRO
output channel status information
from the left channel (subframe A) or the right channel (subframe B). CSLR = 0 selects the left
channel. CSLR = 1 selects the right channel.
Direct Output Signals (Jittered)
Pin Name SSOP
I/O
Description
DLRCLK
24
O
Left/
right
clock derived directly from the biphase-mark input stream. HI for the left channel, LO for
the right channel. T his is a jittered output clock! Use this output to feed one input of the phase
detector of the external analog phase lock loop. See Figure 20 for timing.
Bit clock derived directly from the biphase-mark input stream. Falling edge active (i.e., DSDAT A is
valid on the falling edge of DBCLK ). T his is a jittered output clock! T his clock is gated to produce
24 pulses per sample (left or right) aligned with the data. See Figure 20 for timing.
Serial data derived directly from the biphase-mark input stream. T his is a jittered signal! All 24 bits
are output (20 bits of audio data plus 4 bits of auxiliary data), LSB first. Unlike the SDAT A output
(Pin 21), this output does not hold the last valid sample when the current sample is invalid. See Fig-
ure 20 for timing.
DBCLK
25
O
DSDAT A
23
O
Digital Audio Output Signals (I
2
S-Compatible)
Pin Name SSOP
I/O
Description
LRCLK
20
O
Left/
right
clock for the output serial digital audio stream. HI for the left channel, LO for the right
channel. LRCLK is the external analog PLL voltage controlled oscillator (VCO) output divided
down by 512. Use this low jitter output clock to feed the second input of the phase detector of the
external analog phase lock loop. See Figure 18 for timing.
Bit clock for the output serial digital audio stream. Serial data is valid on the rising edge of BCLK .
T here are 32 bit clock periods for the left sample, and 32 bit clock periods for the right channel (i.e.,
the bit clock frequency is 64
×
FS). BCLK is the external analog PLL VCO output divided down by
8. Use this signal to clock the audio data into downstream DACs, sample rate converters or DSPs.
See Figure 18 for timing.
Serial Audio Data. All 24 bits are output (20 bits audio data plus 4 bits of auxiliary data), MSB first.
When the current sample is invalid, the last valid sample is repeated. See Figure 18 for timing.
BCLK
19
O
SDAT A
21
O
Clock Input Signals
Pin Name SSOP
I/O
Description
ASCLK
6
I
Under normal conditions (when using the AD1895 with an external analog PLL), ASCLK should be
connected to the PLL’s VCO output, which runs at 512
×
FS. If an external PLL is not used (not
normal configuration), ASCLK must be fed with an asynchronous clock at a frequency above 20MHz.
Under normal conditions (when using the AD1895 with an external analog PLL), PCLK should be
connected to the PLL’s VCO output, which runs at 512
×
FS. If an external PLL is not used (not
normal configuration), PCLK should be grounded, which has the effect of shutting off the digital
audio output signals (LRCLK , BCLK and SDAT A) as well.
PCLK
7
I
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1895AYRS | 制造商:Analog Devices 功能描述:Sample Rate Converter 28-Pin SSOP 制造商:Rochester Electronics LLC 功能描述:192KHZ 8:1 STEREO ASYNC SAMPLE RATE CONV - Bulk 制造商:Analog Devices 功能描述:IC STEREO ASR CONVERTER |
| AD1895AYRSRL | 制造商:Analog Devices 功能描述:Sample Rate Converter 28-Pin SSOP T/R |
| AD1895AYRSZ | 功能描述:IC CONV SAMPLE RATE ASYNC 28SSOP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:- 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
| AD1895AYRSZRL | 功能描述:IC SAMP-RATEHP/CONV 24BIT 28SSOP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:- 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
| AD1895YRS | 制造商:Rochester Electronics LLC 功能描述:192KHZ 8:1 STEREO ASYNC S - Bulk |
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