參數(shù)資料
型號(hào)： AD1895
廠商： Analog Devices, Inc.
英文描述： 3 V/5 V Digital Audio Receiver,External APLL(數(shù)字音頻接收器)
中文描述： 3伏/ 5 V數(shù)字音頻接收器，外部美集（數(shù)字音頻接收器）
文件頁數(shù)： 12/16頁
文件大?。?/td> 130K
代理商： AD1895
AD1895
REV. 0
–12–
OPE RAT ING ISSUE S
Non-PLL Mode
It is possible to operate the AD1895 without an external PLL.
T he normally low jitter I
2
S interface will have jitter, which may
be ignored if the AD1895 is used with an asynchronous sample
rate converter (ASRC) such as the AD1890 or AD1893.
T he serial output may be used provided that there is some
external logic which obeys the following constraints. On either
transition of the DLRCLK output signal (Pin 24), the logic
must supply 256 pulses to the PCL K input (Pin 7) at a
frequency high enough to insure that all 256 pulses have been
applied before the next DLRCLK transition. After the 256
pulses have been applied, the logic must stop and wait for the
next DLRCLK transition. T his scheme has the advantage that
the “sample-repeat” feature still works, and the interface
(BCLK [Pin 19], LRCLK [Pin 20], and SDAT A [Pin 21]) is
still I
2
S compatible.
APPLICAT ION ISSUE S
T he recommended application circuit for the AD1895 is shown
in Figure 17.
BIAS
VCO IN
PFD OUT
SELECT
VCO INHIBIT
NC
PFD INHIBIT
VCO OUT
F
IN
–B
F
IN
–A
DVDD
DGND
AVDD
AGND
TEXAS INSTRUMENTS
TLC2932I
+5V
FERRITE
BEAD
2.26k
0.01μF
0.22μF
634k
22.1k
0.1μF
0.01μF
0.1μF
FERRITE
BEAD
8
9
3
5
4
14
11
10
2
6
12
13
7
1
KEEP SHORT
+5V
D TYPE REGISTER
D0
D1
D2
D3
D4
CLK
Q0
Q1
Q2
Q3
Q4
OE
ERROR BIT (NO BIPHASE-MARK INPUT OR LOSS OF LOCK)
TO LEDS,
μCONTROLLER,
DSP, ETC.
USER BIT
CHANNEL STATUS BIT
PARITY BIT
VALIDITY BIT
FROM DSP, μCONTROLLLER,
SWITCH, ETC.
ACTIVE HI RESET
I
2
S SIGNALS
TO DSP, DAC,
TRANSMITTER,
ASRC, ETC.
256 x F
S
CLOCK
DIRECT CP-340
OUTPUT SIGNALS
(JITTERED)
KEEP SHORT
19
21
12
25
23
24
20
7
6
9
18
17
13
14
16
15
BCLK
SDATA
CLK256
DBCLK
DSDATA
DLRCLK
LRCLK
PCLK
ASCLK
RESET
ERROR
PARITY
SFCLK
VBIT
UBIT
CSBIT
AD1895
CA
CB
CC
CD
CE
CON/
PRO
CSCLK
CSLR
RXP
RXN
22
8
DV
DD
DGND
0.01μF
FERRITE
BEAD
+5V
4
3
2
1
28
27
26
5
10
11
0.01μF
0.01μF
110
75
0.01μF
0.01μF
RXP
RXN
10
11
CONSUMER
S/PDIF INPUT
75
COAX
RCA PHONO
CONNECTOR
PROFESSIONAL
AES/EBU INPUT
110
TWISTED PAIR
XLR CONNECTOR
LEFT/RIGHT CHANNEL
STATUS SELECT
D TYPE REGISTER
Q0
Q1
Q2
Q3
Q4
Q5
OE
D0
D1
D2
D3
D4
D5
CLK
TO LEDS,
μCONTROLLER,
DSP, ETC.
FROM DSP,
μCONTROLLER
SWITCH, ETC.
Figure 17. Recommended Application Circuit
T IMING DIAGRAMS
T he AD1895 timing diagrams are shown in Figures 18 through 22.
RIGHT CHANNEL
LEFT CHANNEL
LRCLK
OUTPUT
BCLK
OUTPUT
SDATA
OUTPUT
MSB
MSB–1
MSB–2
LSB+2
LSB+1
LSB
MSB
MSB–1
MSB–2
LSB+2
LSB+1
LSB
MSB
Figure 18. I
2
S Output Format
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD1895AYRS 制造商:Analog Devices 功能描述:Sample Rate Converter 28-Pin SSOP 制造商:Rochester Electronics LLC 功能描述:192KHZ 8:1 STEREO ASYNC SAMPLE RATE CONV - Bulk 制造商:Analog Devices 功能描述:IC STEREO ASR CONVERTER
AD1895AYRSRL 制造商:Analog Devices 功能描述:Sample Rate Converter 28-Pin SSOP T/R
AD1895AYRSZ 功能描述:IC CONV SAMPLE RATE ASYNC 28SSOP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:- 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6
AD1895AYRSZRL 功能描述:IC SAMP-RATEHP/CONV 24BIT 28SSOP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:- 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6
AD1895YRS 制造商:Rochester Electronics LLC 功能描述:192KHZ 8:1 STEREO ASYNC S - Bulk
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