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參數(shù)資料
| 型號： | AD1888JCP-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | DPI 4 MOULEE NOIRE |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, QCC48 |
| 封裝： | MO-220-VKKD-2, LFCSP-48 |
| 文件頁數(shù)： | 25/32頁 |
| 文件大小： | 312K |
| 代理商： | AD1888JCP-REEL |
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REV. 0
AD1888
–25–
Serial Configuration Register (Index 74h)
Reg
No. Name D15
D14
D13
D12
D11
D10 D9 D8
D7 D6
D5 D4 D3 D2
D1
D0
Default
74h Serial
SLOT16
REGM2 REGM1 REGM0 REGM3 DRF
X
Configuration
CHEN
X
LBKS1
LBKS0
INTS
X
SPAL
SPDZ
SPLNK
1001h
All registers not shown and bits containing an X are assumed to be reserved.
Note that this register is not reset when Register 00h (Reset Register) is written to (soft reset).
SPLNK
SPDIF Link. This bit enables the SPDIF to link with the front DACs for data requesting.
0 = SPDIF and DAC are not linked.
1 = SPDIF and DAC are linked and receive the same data requests (reset default).
SPDZ
SPDIF DACZ.
0 = Repeat last sample out of the SPDIF stream if FIFO underruns (reset default).
1 = Forces midscale sample out the SPDIF stream if FIFO underruns.
SPAL
SPDIF ADC Loop-Around.
0 = SPDIF transmitter is connected to the AC-Link stream (reset default).
1= SPDIF transmitter is connected to the digital ADC stream, not the AC-Link.
INTS
Interrupt Mode Select. This bit selects the JS interrupt implementation path.
0 = Bit 0 SLOT 12 (modem interrupt) (reset default).
1 = Slot 6 Valid Bit (MIC ADC interrupt).
LBKS[1:0]
Loop-Back Selection. These bits select the internal digital loop-back path when LPBK bit is active (see Register 20h)
00 = Loop-back through the front DACs (reset default).
01 = Loop-back through the surround DACs.
10 = Reserved
11 = Loop-back through the center and LFE DACs (center DAC loops back from the ADC left channel, the LFE
DAC from the ADC right channel).
CHEN
Chain Enable. This bit enables chaining of a slave codec SDATA_IN stream into the ID0 pin (Pin 45).
0 = Disable chaining (reset default).
1 = Enable chaining into ID0 pin.
DRF
DAC Request Force. This allows the AD1888 to synchronize DAC requests with the AD1981A/B.
0 = Normal DAC requesting sequence (reset default).
1 = Synchronize to AD1981A/B DAC requests.
REGM3
Slave 3 Codec Register Mask
REGM0
Master Codec Register Mask
REGM1
Slave 1 Codec Register Mask
REGM2
Slave 2 Codec Register Mask
SLOT16
Enable 16-Bit Slot Mode. SLOT16 makes all ac-link slots 16 bits in length, formatted into 16 slots. This is a
preferred mode for DSP serial port interfacing.
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相關代理商/技術參數(shù) |
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| AD1888JCPZ | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 6DAC 20-Bit 48-Pin LFCSP EP Tray |
| AD1888JCPZ-REEL | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 6DAC 20-Bit 48-Pin LFCSP EP T/R |
| AD1888JST | 制造商:Analog Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述:LOW COST 6 CHANNELL AC"97 AUDIO CODEC - Tape and Reel |
| AD1888JST-REEL | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 6DAC 20-Bit 48-Pin LQFP T/R |
| AD1888JSTZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:AC 97 SoundMAX Codec |
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