參數(shù)資料
型號(hào)： AD1888JCP-REEL
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： DPI 4 MOULEE NOIRE
中文描述： SPECIALTY CONSUMER CIRCUIT, QCC48
封裝： MO-220-VKKD-2, LFCSP-48
文件頁數(shù)： 14/32頁
文件大小： 312K
代理商： AD1888JCP-REEL
REV. 0
–14–
AD1888
ROV[4:0]
Right PCM Out Volume. Allows setting the PCM right channel attenuator in 32 volume levels. The LSB represents
1.5 dB, and the gain range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
OMRM
Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately
from the AVM bit. Otherwise, this bit will always read 0 and will have no affect when set to 1.
LOV[4:0]
Left PCM Out Volume. Allows setting the PCM left channel attenuator in 32 volume levels. The LSB represents
1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
OM
PCM Out Volume Mute. When this bit is set to 1, both the left and the right channels are muted, unless the
MSPLT bit in Register 76h is set to 1, in which case this mute bit will affect only the left channel.
PCM-Out Volume Register (Index 18h)
Reg
No. Name
D15 D14 D13 D12
D11
D10
D9
D8
D7
D6
D5 D4
D3
D2
D1
D0
Default
18h PCM Out Volume OM X
X
LOV4 LOV3
LOV2
LOV1
LOV0
OMRM
*
X
X
ROV4
ROV3
ROV2 ROV1 ROV0 8808h
*
For AC ’97 compatibility, Bit D7 is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels.
If MSPLT is not set, Bit D7 has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table IV for examples.
Note that depending on the state of the AC97NC bit in Register 76h, this register has the following additional functionality:
For AC97NC = 0, the register also controls the Surround, Center, and LFE DAC Gain/Attenuators.
For AC97NC = 1, the register controls the PCM Out Volume only.
Table IV. Volume Settings for Line-In, CD Volume, AUX, and PCM-Out
Control Bits
Reg. 76h
Line-In (10h), CD (12h), AUX (16h) and PCM-Out (18h)
Left Channel Volume D[12:8]
Right Channel Volume D[4:0]
MSPLT
*
D15 WRITE
READBACK Function
D7
*
WRITE
READBACK
Function
0
0
0
0
1
0
0
0
1
0
0 0000
0 1000
1 1111
x xxxx
1 1111
0 0000
0 1000
1 1111
x xxxx
1 1111
12 dB Gain
0 dB Gain
–34.5 dB Gain
– dB Gain, Muted
–34.5 dB Gain
x
x
x
x
1
0 0000
0 1000
1 1111
x xxxx
x xxxx
0 0000
0 1000
1 1111
x xxxx
x xxxx
12 dB Gain
0 dB Gain
–34.5 dB Gain
– dB Gain, Muted
– dB Gain,
Right Only Muted
–34.5 dB Gain
1
1
x xxxx
x xxxx
– dB Gain,
Left Only Muted
– dB Gain, Left Muted 1
0
1 1111
1 1111
1
1
x xxxx
x xxxx
x xxxx
x xxxx
– dB Gain, Right Muted
*
For AC ’97 compatibility, Bit D7 is only available by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels.
If MSPLT is not set, RM Bit has no effect.
x in the above table is “don’t care.”
Record Select Control Register (Index 1Ah)
Reg
No.
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
1Ah Record Select
X
X
X
X
X
LS2
LS1
LS0
X
X
X
X
X
RS2
RS1
RS0
0000h
All registers not shown and bits containing an X are assumed to be reserved.
Refer to Table V for examples. Used to select the record source independently for the right and left channels. For MIC recording, see MS bit (Register 20h) for MIC1
and MIC2 input selection.
RS [2:0]
Right Record Select
LS [2:0]
Left Record Select
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