參數(shù)資料
型號(hào)： AD1888JCP-REEL
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： DPI 4 MOULEE NOIRE
中文描述： SPECIALTY CONSUMER CIRCUIT, QCC48
封裝： MO-220-VKKD-2, LFCSP-48
文件頁(yè)數(shù)： 22/32頁(yè)
文件大?。?/td> 312K
代理商： AD1888JCP-REEL
REV. 0
–22–
AD1888
SPDIF Control Register (Index 3Ah)
Reg
No.
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
3Ah SPDIF
Control
V
X
SPSR1
SPSR0
L
CC6
CC5
CC4
CC3
CC2
CC1
CC0
PRE
COPY
/AUD PRO
2000h
All registers not shown and bits containing an X are assumed to be reserved.
Register 3Ah is a read/write register that controls SPDIF functionality and manages bit fields propagated as channel status (or subframe in the V case). With the
exception of V, this register should only be written to when the SPDIF transmitter is disabled (SPDIF Bit in Register 2Ah is 0). This ensures that control and status
information starts up correctly at the beginning of SPDIF transmission.
PRO
Professional. 1 indicates professional use of channel status, 0 indicates consumer.
/AUD
Non-Audio. 1 indicates data is non PCM format, 0 indicates data is PCM.
COPY
Copyright. 1 indicates copyright is asserted, 1 indicates copyright is not asserted.
Pre-emphasis. 1 indicates filter pre-emphasis is 50
μ
s/15
μ
s, 0 indicates pre-emphasis is none.
PRE
CC[6-0]
Category Code. Programmed according to IEC standards, or as appropriate.
L
Generation Level. Programmed according to IEC standards, or as appropriate.
SPSR[1,0]
SPDIF Transmit Sample Rate:
SPSR[1:0] = 00 Transmit Sample Rate = 44.1 kHz
SPSR[1:0] = 01 Reserved
SPSR[1:0] = 10 Transmit Sample Rate = 48 kHz (default)
SPSR[1:0] = 11 Not supported.
V
Validity. This bit affects the Validity flag (Bit 28 transmitted in each SPDIF L/R subframe) and enables the SPDIF
transmitter to maintain connection during error or mute conditions.
V = 1 Each SPDIF subframe (L + R) has Bit 28 set to 1. This tags both samples as invalid.
V = 0 Each SPDIF subframe (L + R) has Bit 28 set to 0 for valid data and 1 for invalid data (error condition).
Note that when V = 0, asserting the VFORCE bit (D15) in Register 2Ah (Ext’d Audio Stat/Ctrl) will force the
Validity flag low, marking both samples as valid.
Table VIII. Settings for Surround Register
Control Bits
Surround Volume (38h)
Left Surround D[13:8]
Right Surround D[5:0]
WRITE
00 0000
00 1111
01 1111
1x xxxx
xx xxxx
D15/D7
READBACK
00 0000
00 1111
01 1111
01 1111
xx xxxx
Function with AC97NC = 0
Function with AC97NC = 1
0
0
0
0
1
0 dB Gain
–22 dB Gain
–46.5 dB Gain
–46.5 dB Gain
Muted
12 dB Gain
–10.5 dB Gain
–34.5 dB Gain
Not Applicable
Muted
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