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參數(shù)資料
| 型號： | AD1888JCP-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | DPI 4 MOULEE NOIRE |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, QCC48 |
| 封裝： | MO-220-VKKD-2, LFCSP-48 |
| 文件頁數(shù)： | 15/32頁 |
| 文件大?。?/td> | 312K |
| 代理商： | AD1888JCP-REEL |
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REV. 0
AD1888
–15–
Table V. Settings for Record Select Control
LS [10:8]
Left Record Source
RS [2:0]
Right Record Source
000
001
010
011
100
101
110
111
MIC
CD_L
Muted
AUX_L
LINE_IN_L
Stereo Mix (L)
Mono Mix
PHONE_IN
000
001
010
011
100
101
110
111
MIC
CD_R
Muted
AUX_R
LINE_IN_R
Stereo Mix (R)
Mono Mix
PHONE_IN
RIM[3:0]
Right Input Mixer Gain Control. Each LSB represents 1.5 dB, 0000 = 0 dB, and the gain range is 0 dB to 22.5 dB.
IMRM
Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately
from the IM bit. Otherwise, this bit will always read 0 and will have no effect when set to 1.
LIM[3:0]
Left Input Mixer Gain Control. Each LSB represents 1.5 dB, 0000 = 0 dB, and the gain range is 0 dB to 22.5 dB.
IM
Input Mute. When this bit is set to 1, both the left and the right channels are muted, unless the MSPLT bit in Reg-
ister 76h is set to 1, in which case this mute bit will affect only the left channel.
Table VI. Settings for Record Gain Register
Control Bits
Record Gain (1Ch)
Reg. 76h
Left Channel Input Mixer D[11:8]
Right Channel Input Mixer D[3:0]
MSPLT
*
D15 WRITE
READBACK
Function
D7
*
WRITE
READBACK
Function
0
0
1111
1111
22.5 dB Gain
x
1111
1111
22.5 dB Gain
0
0
0000
0000
0 dB Gain
x
0000
0000
0 dB Gain
0
1
xxxx
xxxx
– dB Gain, Muted
x
xxxx
xxxx
– dB Gain, Muted
1
0
1111
1111
22.5 dB Gain
1
xxxx
xxxx
– dB Gain,
Right Only Muted
1
1
xxxx
xxxx
– dB Gain,
Left Only Muted
0
1111
1111
22.5 dB Gain
1
1
xxxx
xxxx
– dB Gain,
Left Muted
1
xxxx
xxxx
– dB Gain, Right Muted
*
For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right
channels. If MSPLT is not set, Bit D7 has no effect.
x is “don’t care.”
Record Gain Register (Index 1Ch)
Reg
No.
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
1Ch Record Gain
IM
X
X
X
LIM3
LIM2
LIM1
LIM0 IMRM
*
X
X
X
RIM3
RIM2
RIM1 RIM0 8000h
*
For AC ’97 compatibility, Bit D7 is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels.
If MSPLT is not set, Bit D7 has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table VI for examples.
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