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參數(shù)資料
| 型號： | AD1870 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Single-Supply 16-Bit Stereo ADC |
| 中文描述： | 單電源16位立體聲ADC |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 276K |
| 代理商： | AD1870 |
AD1870
REV. 0
–15–
BCLK
RDEDGE = LO
BCLK
RDEDGE = HI
32
1
2
3
4
17
SOUT
OUTPUT
WCLK
OUTPUT
TAG
OUTPUT
MSB
LEFT TAG
MSB
RIGHT TAG
31
32
1
2
3
4
17
MSB-1
LEFT DATA
MSB-2
LSB
MSB-1
RIGHT DATA
MSB
MSB-2
LSB
ZEROS
ZEROS
ZEROS
INPUT
L
R
CK
INPUT
5
5
MSB
LSB
LSB
Figure 10. Serial Data Output Timing: Slave Mode, I
2
S-Justified, S/
M
= Hl, R
L
JUST = LO,
MSBDLY
= LO
BCLK
RDEDGE = LO
OUTPUT
BCLK
RDEDGE = HI
31
32
1
2
15
16
17
18
19
32
1
2
15
16
17
18
19
32
1
2
MSB-14
LSB
PREVIOUS DATA
MSB-1
LEFT DATA
MSB-2
LSB
RIGHT DATA
MSB
SOUT
OUTPUT
ZEROS
ZEROS
MSB-1 MSB-2
LSB
ZEROS
WCLK
OUTPUT
TAG
OUTPUT
MSB
LSB
LEFT TAG
MSB
LSB
RIGHT TAG
MSB
LSB
LEFT TAG
L
R
CK
OUTPUT
MSB
Figure 11. Serial Data Output Timing: Master Mode, Right-Justified with No MSB Delay, S/
M
= LO,
R
L
JUST = Hl,
MSBDLY
= Hl
BCLK
RDEDGE = LO
OUTPUT
BCLK
RDEDGE = HI
32
1
2
16
17
18
19
1
2
16
17
18
19
20
1
2
MSB-14
LSB
PREVIOUS DATA
MSB-1
LEFT DATA
MSB-2
LSB
RIGHT DATA
SOUT
OUTPUT
ZEROS
ZEROS
MSB-1 MSB-2
LSB
ZEROS
WCLK
OUTPUT
TAG
OUTPUT
MSB
LSB
LEFT TAG
MSB
LSB
RIGHT TAG
20
L
R
CK
OUTPUT
MSB
MSB
Figure 12. Serial Data Output Timing. Master Mode, Right-Justified with MSB Delay,
WCLK Pulsed in 17th BCLK Cycle, S/
M
= LO, R
L
JUST = Hl,
MSBDLY
= LO
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1870_02 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Single-Supply 16-Bit Stereo ADC |
| AD1870AR | 制造商:Analog Devices 功能描述:ADC Dual Delta-Sigma 48ksps 16-bit Serial 28-Pin SOIC W 制造商:Rochester Electronics LLC 功能描述:SINGLE ENDED, DUAL CHANNEL ADC - Bulk |
| AD1870AR-REEL | 制造商:Analog Devices 功能描述:ADC Dual Delta-Sigma 48ksps 16-bit Serial 28-Pin SOIC W T/R 制造商:Rochester Electronics LLC 功能描述:SINGLE ENDED, DUAL CHANNEL ADC - Tape and Reel |
| AD1870ARZ | 制造商:Analog Devices 功能描述:ADC Dual Delta-Sigma 48ksps 16-bit Serial 28-Pin SOIC W |
| AD1870ARZ-REEL | 制造商:Analog Devices 功能描述: |
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