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參數(shù)資料
| 型號(hào)： | AD1870 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Single-Supply 16-Bit Stereo ADC |
| 中文描述： | 單電源16位立體聲ADC |
| 文件頁(yè)數(shù)： | 13/20頁(yè) |
| 文件大小： | 276K |
| 代理商： | AD1870 |
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AD1870
REV. 0
–13–
Timing Parameters
For master modes, a BCLK transmitting edge (labeled
“
XMIT
”
)
will be delayed from a CLKIN rising edge by t
DLYCKB
, as shown
in Figure 17. A L
R
CK transition will be delayed from a BCLK
transmitting edge by t
DLYBLR
. A WCLK rising edge will be
delayed from a BCLK transmitting edge by t
DLYBWR
, and a WCLK
falling edge will be delayed from a BCLK transmitting edge by
t
DLYBWF
. The DATA and TAG outputs will be delayed from a
transmitting edge of BCLK by t
DLYDT
.
For slave modes, an L
R
CK transition must be setup to a BCLK
sampling edge (labeled
“
SAMPLE
”
) by t
SETLRBS
. The DATA
and TAG outputs will be delayed from an L
R
CK transition by
t
DLYLRDT
, and DATA and TAG outputs will be delayed from
BCLK transmitting edge by t
DLYBDT
. For
“
Slave Mode, Data
Position Controlled by WCLK Input,
”
WCLK must be set up
to a BCLK sampling edge by t
SETWBS
.
For both master and slave modes, BCLK must have a minimum
LO pulsewidth of t
BPWL
, and a minimum HI pulsewidth of t
BPWH
.
The AD1870 CLKIN and
RESET
timing is shown in Figure
19. CLKIN must have a minimum LO pulsewidth of t
CPWL
, and
a minimum HI pulsewidth of t
CPWH
. The minimum period of
CLKIN is given by t
CLKIN
.
RESET
must have a minimum LO
pulsewidth of t
RPWL
. Note that there are no setup or hold time
requirements for
RESET
.
Master Clock (CLKIN) Considerations
It is recommended that the BCLK and L
R
CK are derived from
CLKIN to ensure correct phase relationships. The modulator
of the AD1870 runs at 64
×
f
S
, therefore best performance is
obtained when the BCLK rate equals 64
×
f
S
or 32
×
f
S
. BCLK
rates such as 48
×
f
S
may result in an increased spectral noise
floor, depending on the phase relationship of BCLK to CLKIN.
Synchronizing Multiple AD1870s
Multiple AD1870s can be synchronized by making all the
AD1870s serial port slaves. This option is illustrated in Figure 6.
See the
“
Reset, Autocalibration, and Power Down
”
section for
additional information.
#1 AD1870
SLAVE MODE
CLKIN
DATA
BCLK
WCLK
L
R
CK
CLOCK
SOURCE
#2 AD1870
SLAVE MODE
CLKIN
DATA
BCLK
WCLK
L
R
CK
#N AD1870
SLAVE MODE
CLKIN
DATA
BCLK
WCLK
L
R
CK
RESET
RESET
RESET
Figure 6. Synchronizing Multiple AD1870s
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1870_02 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Single-Supply 16-Bit Stereo ADC |
| AD1870AR | 制造商:Analog Devices 功能描述:ADC Dual Delta-Sigma 48ksps 16-bit Serial 28-Pin SOIC W 制造商:Rochester Electronics LLC 功能描述:SINGLE ENDED, DUAL CHANNEL ADC - Bulk |
| AD1870AR-REEL | 制造商:Analog Devices 功能描述:ADC Dual Delta-Sigma 48ksps 16-bit Serial 28-Pin SOIC W T/R 制造商:Rochester Electronics LLC 功能描述:SINGLE ENDED, DUAL CHANNEL ADC - Tape and Reel |
| AD1870ARZ | 制造商:Analog Devices 功能描述:ADC Dual Delta-Sigma 48ksps 16-bit Serial 28-Pin SOIC W |
| AD1870ARZ-REEL | 制造商:Analog Devices 功能描述: |
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