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參數(shù)資料
| 型號： | AD1870 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Single-Supply 16-Bit Stereo ADC |
| 中文描述： | 單電源16位立體聲ADC |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 276K |
| 代理商： | AD1870 |
AD1870
REV. 0
–12–
Serial Port Data Timing Sequences
The RDEDGE input (Pin 6) selects the bit clock (BCLK) polarity.
RDEDGE HI causes data to be transmitted on the BCLK falling
edge and valid on the BCLK rising edge; RDEDGE LO causes
data to be transmitted on the BCLK rising edge and valid on
the BCLK falling edge. This is shown in the serial data output
timing diagrams. The term
“
sampling
”
is used generically to
denote the BCLK edge (rising or falling) on which the serial data is
valid. The term
“
transmitting
”
is used to denote the other BCLK
edge. The S/
M
input (Pin 7) selects slave mode (S/
M
HI) or
master mode (S/
M
LO). Note that in slave mode, BCLK may be
continuous or gated (i.e., a stream of pulses during the data phase
followed by periods of inactivity between channels).
In the master modes, the bit clock (BCLK), the left/right clock
(L
R
CK), and the word clock (WCLK) are always outputs, gen-
erated internally in the AD1870 from the master clock (CLKIN)
input. In master mode, a L
R
CK cycle defines a 64-bit
“
frame.
”
L
R
CK is HI for a 32-bit
“
field
”
and L
R
CK is LO for a 32-
bit
“
field.
”
In the slave modes, the bit clock (BCLK), and the left/right clock
(L
R
CK) are user-supplied inputs. The word clock (WCLK) is an
internally generated output except when S/
M
is HI, R
L
JUST is
HI, and
MSBDLY
is LO, when it is a user-supplied input that
controls the data position. Note that the AD1870 does not sup-
port asynchronous operation in slave mode; the clocks (CLKIN,
L
R
CK, BCLK and WCLK) must be externally derived from a
common source. In general, CLKIN should be divided down
externally to create L
R
CK, BCLK, and WCLK.
In the slave modes, the relationship between L
R
CK and BCLK
is not fixed, to the extent that there can be an arbitrary number
of BCLK cycles between the end of the data transmission and
the next L
R
CK transition. The slave mode timing diagrams are
therefore simplified as they show precise 32-bit fields and
64-bit frames.
In two slave modes, it is possible to pack two 16-bit samples in
a single 32-bit frame, as shown in Figures 15 and 16. BCLK,
L
R
CK, DATA, and TAG operate at one-half the frequency
(twice the period) as in the 64-bit frame modes. This 32-bit
frame mode is enabled by pulsing the L
R
CK HI for a minimum
of one BCLK period to a maximum of sixteen BCLK periods.
The L
R
CK HI for one BCLK period case is shown in Fig-
ures 15 and 16. With a one or two BCLK period HI pulse on
L
R
CK, note that both the left and right TAG bits are output
immediately, back-to-back. With a three-to-sixteen BCLK period
HI pulse on L
R
CK, the left TAG bits are followed by one to
fourteen
“
dead
”
cycles (i.e., zeros) followed by the right TAG
bits. Also note that WCLK stays HI continuously when the
AD1870 is in the 32-bit frame mode. Figure 15 illustrates the
left-justified case, while Figure 16 illustrates the I
2
S-justified case.
In all modes, the left and right channel data is updated with the
next sample within the last 1/8 of the current conversion cycle (i.e.,
within the last 4 BCLK cycles in 32-bit frame mode, and within
the last 8 BCLK cycles in 64-bit frame mode). The user must con-
strain the output timing such that the MSB of the right channel
is read before the final 1/8 of the current conversion period.
Two modes deserve special discussion. The first special mode,
“
Slave Mode, Data Position Controlled by WCLK Input
”
(S/
M
= HI, R
L
JUST = HI,
MSBDLY
= LO), shown in Figure 8, is
the only mode in which WCLK is an input. The 16-bit output
data words can be placed at user-defined locations within 32-bit
fields. The MSB will appear in the BCLK period after WCLK is
detected HI by the BCLK sampling edge. If WCLK is HI dur-
ing the first BCLK of the 32-bit field (if WCLK is tied HI for
example), then the MSB of the output word will be valid on the
sampling edge of the second BCLK. The effect is to delay the
MSB for one bit clock cycle into the field, making the output
data compatible at the data format level with the I
2
S data for-
mat. Note that the relative placement of the WCLK input can
vary from 32-bit field to 32-bit field, even within the same
64-bit frame. For example, within a single 64-bit frame, the left
word could be right justified (by pulsing WCLK HI on the 16th
BCLK) and the right word could be in an I
2
S-compatible data
format (by having WCLK HI at the beginning of the second field).
In the second special mode
“
Master Mode, Right-Justified
with MSB Delay, WCLK Pulsed in 17th Cycle
”
(S/
M
= LO,
R
L
JUST = HI,
MSBDLY
= LO), shown in Figure 12, WCLK
is an output and is pulsed for one cycle by the AD1870. The
MSB is valid on the 18th BCLK sampling edge, and the LSB
extends into the first BCLK period of the next 32-bit field.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD1870_02 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Single-Supply 16-Bit Stereo ADC |
| AD1870AR | 制造商:Analog Devices 功能描述:ADC Dual Delta-Sigma 48ksps 16-bit Serial 28-Pin SOIC W 制造商:Rochester Electronics LLC 功能描述:SINGLE ENDED, DUAL CHANNEL ADC - Bulk |
| AD1870AR-REEL | 制造商:Analog Devices 功能描述:ADC Dual Delta-Sigma 48ksps 16-bit Serial 28-Pin SOIC W T/R 制造商:Rochester Electronics LLC 功能描述:SINGLE ENDED, DUAL CHANNEL ADC - Tape and Reel |
| AD1870ARZ | 制造商:Analog Devices 功能描述:ADC Dual Delta-Sigma 48ksps 16-bit Serial 28-Pin SOIC W |
| AD1870ARZ-REEL | 制造商:Analog Devices 功能描述: |
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