參數(shù)資料
型號(hào)： AD1870
廠商： Analog Devices, Inc.
英文描述： Single-Supply 16-Bit Stereo ADC
中文描述： 單電源16位立體聲ADC
文件頁(yè)數(shù)： 11/20頁(yè)
文件大?。?/td> 276K
代理商： AD1870
AD1870
REV. 0
–11–
Shown in Figure 5 is a circuit for obtaining a 3 dB improve-
ment in dynamic range by using both channels of a single AD1870
with a mono input. A stereo implementation would require
using two AD1870s and using the recommended input structure
shown in Figure 2. Note that a single microprocessor would likely
be able to handle the averaging requirements for both left and
right channels.
AD1870
RECOMMENDED
INPUT BUFFER
SINGLE
CHANNEL
INPUT
DIGITAL
AVERAGER
AD1870
V
IN
R
V
IN
L
SINGLE
CHANNEL
OUTPUT
Figure 5. Increasing Dynamic Range By Using Two
AD1870 Channels
DIGITAL INTERFACE
Modes of Operation
The AD1870
’
s flexible serial output port produces data in
two
’
s-complement, MSB-first format. The input and output sig-
nals are TTL-logic-level-compatible. Time multiplexed serial
data is output on SOUT (Pin 26), left channel then right chan-
nel, as determined by the left/right clock signal L
R
CK (Pin 1).
Note that there is no method for forcing the right channel to
precede the left channel. The port is configured by pin selec-
tions. The AD1870 can operate in either master or slave mode,
with the data in right-justified, I
2
S-compatible, Word Clock
controlled or left-justified positions.
The various mode options are pin-programmed with the S/
M
(Slave/
Master
) Pin (7), the Right/
Left
Justify Pin (21), and the
MSBDLY
Pin (22). The function of these pins is summarized
as follows:
S/
M
R
L
JUST
MSBDLY
WCLK
BCLK
L
R
CK
Serial Port Operation Mode
1
1
1
Output
Input
Input
Slave Mode. WCLK frames the data. The MSB is output on the
17th BCLK cycle. Provides right-justified data in slave mode
with a 64
×
f
S
BCLK frequency. See Figure 7.
Slave Mode. The MSB is output in the BCLK cycle after
WCLK is detected HI. WCLK is sampled on the BCLK active
edge, with the MSB valid on the next BCLK active edge. Tying
WCLK HI results in I
2
S-justified data. See Figure 8.
1
1
0
Input
Input
Input
1
0
1
Output
Input
Input
Slave Mode. Data left-justified with WCLK framing the data.
WCLK rises immediately after an L
R
CK transition. The MSB is
valid on the first BCLK active edge. See Figure 9.
Slave Mode. Data I
2
S-justified with WCLK framing the data.
WCLK rises in the second BCLK cycle after an L
R
CK transi-
tion. The MSB is valid on the second BCLK active edge. See
Figure 10.
1
0
0
Output
Input
Input
0
1
1
Output
Output
Output
Master Mode. Data right-justified. WCLK frames the data,
going HI in the 17th BCLK cycle. BCLK frequency = 64
×
f
S
.
See Figure 11.
0
1
0
Output
Output
Output
Master Mode. Data right-justified + 1. WCLK is pulsed in the
17th BCLK cycle, staying HI for only 1 BCLK cycle. BCLK
frequency = 64
×
f
S
. See Figure 12.
Master Mode. Data left-justified. WCLK frames the data.
BCLK frequency = 64
×
f
S
. See Figure 13.
Master Mode. Data I
2
S-justified. WCLK frames the data.
BCLK frequency = 64
×
f
S
. See Figure 14.
0
0
1
Output
Output
Output
0
0
0
Output
Output
Output
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