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參數(shù)資料
| 型號： | AD1843JST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Serial-Port 16-Bit SoundComm Codec |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 8/64頁 |
| 文件大?。?/td> | 848K |
| 代理商： | AD1843JST |
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REV. 0
–8–
AD1843
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
100
76
AD1843
TOP VIEW
(Not to Scale)
S
S
N
G
V
D
C
C
N
N
N
N
V
D
V
D
V
D
V
D
B
G
C
C
B
G
G
B
X
X
GNDD
XCTL1
NC
XCTL0
SYNC3
SYNC2
SYNC1
NC
GNDD
V
DD
RESET
PWRDWN
NC
V
DD
PDMNFT
NC
GNDA
HPOUTL
HPOUTC
HPOUTR
V
CC
SUML
SUMR
NC
V
CC
N
N
N
N
N
G
A
F
A
F
L
L
L
L
L
L
L
L
L
M
L
G
C
V
R
G
NC
V
DD
V
CC
NC
NC
NC
NC
SDO
SDFS
GNDD
TSI
TSO
GNDD
V
DD
CS
BM
AUX3R
AUX3L
AUX2R
AUX2L
AUX1R
AUX1L
MICL
MICR
MIN
NC = NO CONNECT
Serial Interface (Continued)
Pin Name
PQFP
TQFP
I/O
Description
CS
9
11
I
Chip Select. When CS is set HI, the serial interface I/O pins will be in their normal
active states. When CS is reset LO, SCLK, SDFS, and SDO are three-
stated; SCLK, SDFS and SDI inputs are ignored; and TSO drives out the logic
level received on TSI.
Time Slot Output. TSO is asserted HI by the AD1843 simultaneously with the LSB
of the last time slot used by the AD1843. It is used to daisy-chain multiple AD1843s
on a common TDM serial bus. If the power-down (
PWRDWN
) pin is asserted or if
the chip select pin (CS) is deasserted, TSO is set to the logic level on the TSI pin,
allowing powered-down or unselected AD1843s on a daisy-chain to be skipped.
Time Slot Input. Asserting TSI HI indicates to the AD1843 that it should use
the next six time slots beginning on the next SCLK period. It also enables TSO
to be asserted at the end of these six time slots. TSI is ignored (but should be tied
LO) when the AD1843 is the bus master since the bus master uses the first time
slots in a TDM frame.
External Control. These signals reflect the status of bits (Data 8 and 9) in Control
Register Address 28 of the AD1843. They may be used for signaling or controlling
external logic.
TSO
6
7
O
TSI
5
6
I
XCTL[1:0]
59, 58
72, 74
I/O
PIN CONFIGURATIONS
100-Lead TQFP
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1845 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Parallel-Port 16-Bit SoundPort Stereo Codec |
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| AD1845JP-REEL | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 68-Pin PLCC T/R |
| AD1845JPZ | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 68-Pin PLCC |
| AD1845JST | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 100-Pin LQFP 制造商:Analog Devices 功能描述:IC CODEC 16-BIT AUDIO |
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