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參數(shù)資料
| 型號： | AD1843JST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | Serial-Port 16-Bit SoundComm Codec |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 14/64頁 |
| 文件大?。?/td> | 848K |
| 代理商： | AD1843JST |
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REV. 0
–14–
AD1843
representations in all four formats correspond to equivalent full-
scale signals. The eight least-significant bit positions of 8-bit
data in 16-bit fields are ignored on input and zeroed on output.
The 16-bit PCM data format is capable of representing 96 dB of
dynamic range. Eight-bit PCM can represent 48 dB of dynamic
range. Companded
μ
-law and A-law data formats use nonlinear
coding with less precision for large-amplitude signals. The loss
of precision is compensated for by an increase in dynamic range
to 64 dB and 72 dB, respectively.
On input, 8-bit companded data is expanded to an internal lin-
ear representation, according to whether
μ
-law or A-law was
specified in the Codec’s internal registers. Note that when
μ
-
law compressed data is expanded to a linear format, it requires
14 bits. A-law data expanded requires 13 bits.
MSB
LSB
COMPRESSED
INPUT DATA
8 7
0
15
MSB
LSB
3/2 2/1
0
15
EXPANSION
MSB
LSB
3/2 2/1
0
15
DAC INPUT
000/00
Figure 4.
μ
-Law or A-Law Expansion
When 8-bit companding is specified, the ADCs’ linear output is
compressed to the format specified.
MSB
LSB
0
15
ADC OUTPUT
MSB
LSB
3/2 2/1
0
15
TRUNCATION
MSB
LSB
8 7
0
15
COMPRESSION
00000000
.
Figure 5.
μ
-Law or A-Law Compression
Note that all format conversions take place at input or output.
Power Supplies and Voltage Reference
The AD1843 operates from either +5.0 V analog (V
CC
) and
digital (V
DD
) power supplies or +5.0 V analog and +3.0 V digi-
tal supplies. Independent analog and digital supplies are recom-
mended for optimal performance though excellent results can be
obtained in single-supply systems. A voltage reference is included
on the Codec and its +2.25 V buffered output is available on an
external pin (CMOUT). The reference output can be used for
biasing op amps used in single supply systems. The internal ref-
erence is externally bypassed to analog ground at the V
REF
pin.
Clocks and Sample Rates
The AD1843 operates from a single external clock or crystal
source. From a single clock, a wide range of sample rates can be
generated. When supplied with a single 24.576 MHz clock, the
AD1843 can be programmed to generate any sample frequency
between 4 kHz and 54 kHz with 1 Hz resolution. For modem
sample rate support, the frequency programmed can also be in-
creased by 8/7 using a control bit. All sample rate changes can
be made “on the fly.”
The AD1843’s SYNC inputs can be used to synchronize the
sampling activity of the four on-chip conversion resources to ex-
ternal clock signals, such as video HSYNC or an ISDN network
clock. The SYNC inputs are used by three on-chip digital phase
filtered in the analog domain by a combination of switched-capaci-
tor and continuous-time filters. They remove the very high fre-
quency components of the DAC bitstream output. No external
components are required. Phase linearity at the analog output is
achieved by internally compensating for the group delay varia-
tion of the analog output filters.
Changes in DAC output attenuation may be programmed to
take effect immediately, or only on zero crossings of the digital
signal, thereby eliminating “zipper” noise on playback. Each
channel has its own independent zero-crossing detector and at-
tenuator change control circuitry. A timer guarantees that re-
quested volume changes will occur even in the absence of an
input signal that changes sign. The time-out period is 8 milli-
seconds at a 48 kHz sampling rate and 48 milliseconds at an
8 kHz sampling rate. (Time-out [ms]
≈
384
÷
F
S
[kHz]).
Digital Mixing
Stereo digital output from the ADCs can be mixed digitally with
the input to the DACs. Digital output from the ADCs going
out of the serial port is unaffected by this digital mix. Along the
digital mix datapath, the 16-bit linear output from the ADCs is
attenuated by an amount specified with Control Register bits.
The level of attenuation applied to the left and right channels is
independently programmable. (Note that internally the AD1843
always works with 16-bit PCM linear data, digital mixing in-
cluded; format conversions take place at the input and output.)
Sixty-four steps of –1.5 dB attenuation are supported to –94.5 dB.
The digital mix datapath can also be completely muted, pre-
venting any mixing of the analog input with the analog output.
Note that the level of the mixed signal is also a function of the
input PGA settings, since they affect the ADCs’ output. The
sample rate of the ADCs and the selected DAC pair must be the
same for the digital mix function to operate properly.
The attenuated digital mix data is digitally summed with the
DAC input data prior to the DACs’ datapath attenuators. The
digital sum of digital mix data and DAC input data is clipped at
plus or minus full scale and does not wrap around. Because
both stereo signals are mixed before the output attenuators,
mix data is attenuated a second time by the DACs’ datapath
attenuators. In case the AD1843 is playing back data but input
digital DAC data fails to arrive in time (“DAC underrun”), then
a midscale zero will be added to the digital mix data in place of
the unavailable DAC data.
Analog Outputs
The two mixer line-level outputs are available at external pins.
Each output channel can be independently muted. When
muted, the outputs will settle to a dc value near CMOUT, the
midscale reference voltage. The two DAC2 stereo outputs are
available at external pins differentially. The full-scale level on
these pins is established by programming bits in a Control Reg-
ister. In addition, there is stereo headphone output (with a cur-
rent return), and a mono output. Both the headphone output
and the mono output have a single mute control.
Digital Data Types
The AD1843 supports four data types: 16-bit twos-complement
linear PCM, 8-bit unsigned linear PCM, 8-bit companded
μ
-law,
and 8-bit companded A-law, as specified by control register bits.
The data type is independently assignable for each conversion
resource (i.e., ADCL, ADCR, DAC1 and DAC2). Data in all
four formats is always transferred MSB first. Eight-bit data is al-
ways left-justified in 16-bit fields; said in other words, the MSBs
of all data types are always aligned; in yet other words, full-scale
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