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參數(shù)資料
| 型號(hào)： | AD1843JST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Serial-Port 16-Bit SoundComm Codec |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, TQFP-100 |
| 文件頁(yè)數(shù)： | 57/64頁(yè) |
| 文件大?。?/td> | 848K |
| 代理商： | AD1843JST |
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AD1843
REV. 0
–57–
MOUT
CMBUF
10k
10k
1/2
OP279
16
OPTIONAL
TO PC
SPEAKER
470μF
Figure 26. AD1843 Mono Output Circuit
Figure 27 illustrates reference bypassing. V
REF
should only be
connected to its bypass capacitors. The 10
μ
F capacitor should
be tantalum, and the 0.1
μ
F capacitor should be ceramic. Figure
27 shows an optional voltage follower buffer on the CMOUT
signal. The output of this buffer, CMBUF, can be used in any
circuit which needs the common-mode bias point from the
AD1843’s on-chip voltage reference. The AD820 is a JFET in-
put op amp whose very high impedance inputs present essen-
tially no load on the CMOUT output from the AD1843.
V
REF
10μF
0.1μF
CMOUT
10μF
0.1μF
CMBUF
1/2
AD820
OPTIONAL BUFFER
Figure 27. AD1843 Voltage Reference Bypassing
Figure 28 illustrates the signal-path filtering capacitors, FILTL
and FILTR, connections to analog ground. The 1.0
μ
F capaci-
tors required by the AD1843 can be of any type.
1.0μF
FILTL
1.0μF
FILTR
Figure 28. AD1843 External Filter Capacitor Connections
Figure 29 illustrates the antialias filtering capacitors, AAFILTL
and AAFILTR, connections to analog ground. The 1000 pF
capacitors must be NPO types.
1000pF
NPO
AAFILTL
AAFILTR
1000pF
NPO
Figure 29. AD1843 Antialias Filter Capacitor Connections
The 24.576 MHz crystal shown in the crystal connection cir-
cuitry of Figure 30 should be fundamental-mode and parallel-
tuned. Note that using the exact data sheet frequency is not
required and that external clock sources can be used in place of
the AD1843’s internal oscillator. If using an external clock
source, apply it to the crystal input pin (XTALI) while leaving
the crystal output pin (XTALO) unconnected. Attention
24.576 MHz
XTALI
XTALO
20–64pF
20–64pF
Figure 30. AD1843 Crystal Connections
should be paid to providing a low-jitter external input clock.
Ideally, there should be no greater than 5 ns rms of random
(white) phase jitter to ensure that it does not significantly de-
grade the SNR of the AD1843.
Figure 31 and Figure 32 show example circuits for a Data
Access Arrangement (DAA). These circuits are shown as
examples only; DAA circuits are subject to regulatory approval
since they connect directly to the Public Switched Telephone
Network (PSTN).
220
SSI 73M9001
TXA
TXA/
MONSUM
TIP
RING
OH/
RLY2/
AG0
AG1
POWER/
RXA
SPK
SPK/
TRAN1
TRAN2
RI/
REOUT1
REOUT2
VCCA
VCCD
AGND
DGND
23
22
15
29
2
8
7
14
17
18
LO
HI
LO
6
21
12
11
1
30
19
9
13
16
10
20
+5VA
V
CC
56k
TO AD1843
XCTL0
RING
INDICATION
TO HOST
INTERRUPT
1
2
3
4
5
6
J1
RJ11
SINGLE
PHONE
COIL
220μF
TO
AD1843 LINLP
TO
AD1843 MIN
LOUT2LN
LOUT2LP
V
CC
FROM AD1843
COIL
Figure 31. Silicon Systems DAA Example Circuit
Figure 32. Cermetek DAA Example Circuit
XMIT+
XMIT–
RCV
OFFHK
RT
TIP
RING
V
CC
GND
CERMETEK
DAA
C3 100nF
C2 100nF
C1 100nF
LOUT2LP
LOUT2LN
LINLP
XCTL0
8
6
5
3
4
U3B4
3
SN74HC14
U3A2
1
SN74HC14
AD1843
C4 100nF
DV
DD
9
1
2
EARTH
VR1
VR3
VR2
CUF1
LIMIT
CLIMIT
C1.5kV
C5, 1nF
RING (RED)
TIP (GREEN)
6
5
4
3
2
1
RJ-1J1
U3D
8
9
SN74HC14
U3C
6
5
SN74HC14
DV
DD
R1
IRQ
CPU INTERRUPT
+ C7
4.7μF TANT
NOTES:
MOV SIDACTORS. AVAILABLE AS A SINGLE UNIT FROM
TECCOR, PART NUMBER P3203AB OR P3203AA.
2. C5,6. EMI/RFI SUPPRESSION. HIGH VOLTAGE DISK
3. F1,2. CURRENT LIMITING DEVICES. RAYCHEM POLY FUSE,
A 10 OHM, 1/8W CARBON FILM RESISTOR MAY BE USED.
4. L1,2. EMI/RFI SUPPRESSION. FERRITE BEADS, FAIR-RITE
5. J1. FCC APPROVED RJ-11 JACK. REF FCC PUBLIC NOTICE #42269
INDL1
INDL2
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