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參數(shù)資料
| 型號(hào)： | AD14160 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Quad-SHARC DSP Multiprocessor Family |
| 中文描述： | 四SHARC處理器DSP的多處理器家族 |
| 文件頁數(shù)： | 20/52頁 |
| 文件大?。?/td> | 1193K |
| 代理商： | AD14160 |
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AD14160/AD14160L
–20–
REV. A
40 MHz–5 V
40 MHz–3.3 V
Min
Parameter
Min
Max
Max
Units
Timing Requirements:
t
SSDATI
t
HSDATI
t
DAAK
Data Setup Before CLKIN
Data Hold After CLKIN
ACK Delay After Address,
MS
x,
SW
,
BMS
1, 2
ACK Setup Before CLKIN
2
ACK Hold After CLKIN
3.5 + DT/8
3.5 – DT/8
3.5 + DT/8
3.5 – DT/8
ns
ns
13 + 7 DT/8 + W
13 + 7 DT/8 + W
ns
ns
ns
t
SACKC
t
HACKC
7 + DT/4
–1 – DT/4
7 + DT/4
–1 – DT/4
Switching Characteristics:
t
DADRO
Address,
MS
x,
BMS
,
SW
Delay
After CLKIN
1
Address,
MS
x,
BMS
,
SW
Hold
After CLKIN
PAGE Delay After CLKIN
RD
High Delay After CLKIN
WR
High Delay After CLKIN
RD
/
WR
Low Delay After CLKIN
Data Delay After CLKIN
Data Disable After CLKIN
3
ADRCLK Delay After CLKIN
ADRCLK Period
ADRCLK Width High
ADRCLK Width Low
8 – DT/8
8 – DT/8
ns
t
HADRO
–1 – DT/8
9 + DT/8
–2 – DT/8
–3 – 3DT/16
8 + DT/4
–1 – DT/8
9 + DT/8
–2 – DT/8
–3 – 3DT/16
8 + DT/4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
DPGC
t
DRDO
t
DWRO
t
DRWL
t
SDDATO
t
DATTR
t
DADCCK
t
ADRCK
t
ADRCKH
t
ADRCKL
16.5 + DT/8
5 – DT/8
5 – 3DT/16
13.5 + DT/4
20 + 5DT/16
8 – DT/8
10.5 + DT/8
16.5 + DT/8
5 – DT/8
5 – 3DT/16
13.5 + DT/4
20 + 5DT/16
8 – DT/8
10.5 + DT/8
0 – DT/8
4 + DT/8
t
CK
(t
CK
/2 – 2)
(t
CK
/2 – 2)
0 – DT/8
4 + DT/8
t
CK
(t
CK
/2 – 2)
(t
CK
/2 – 2)
W = (number of Wait states specified in WAIT register)
×
t
CK
.
NOTES
1
For
MS
x,
SW
,
BMS
, the falling edge is referenced.
2
ACK Delay/Setup: User must meet t
DAAK
or t
DSAK
or synchronous specification t
SACKC
.
3
See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
Synchronous Read/Write—Bus Master
Use these specifications for interfacing to external memory
systems that require CLKIN—relative timing or for accessing a
slave ADSP-2106x (in multiprocessor memory space). These
synchronous switching characteristics are also valid during asyn-
chronous memory reads and writes (see Memory Read—Bus
Master and Memory Write—Bus Master).
When accessing a slave ADSP-2106x, these switching character-
istics must meet the slave’s timing requirements for synchronous
read/writes (see Synchronous Read/Write—Bus Slave). The
slave ADSP-2106x must also meet these (bus master) timing
requirements for data and acknowledge setup and hold times.
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PDF描述 |
|---|---|
| AD14160BB-4 | Quad-SHARC DSP Multiprocessor Family |
| AD14160L | Quad-SHARC DSP Multiprocessor Family |
| AD14160LBB-4 | ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86% |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD14160BB-4 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD14160KB-4 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD14160L | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad-SHARC DSP Multiprocessor Family |
| AD14160LBB-4 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad-SHARC DSP Multiprocessor Family |
| AD14160LKB-4 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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