參數(shù)資料
型號(hào)： AD14160
廠商： Analog Devices, Inc.
英文描述： Quad-SHARC DSP Multiprocessor Family
中文描述： 四SHARC處理器DSP的多處理器家族
文件頁(yè)數(shù)： 11/52頁(yè)
文件大?。?/td> 1193K
代理商： AD14160
AD14160/AD14160L
–11–
REV. A
Pin
Type
I/O/T
2
Function
BMSBCD
Boot Memory Select.
Output:
Used as chip select for boot EPROM devices (when EBOOTBCD = 1,
LBOOTBCD = 0). In a multiprocessor system, BMS is output by the bus master.
Input:
When low,
indicates that no booting will occur and that SHARC_B, C, D will begin executing instructions from
external memory. See table below. This input is a system configuration selection which should be
hardwired.
EBOOT
LBOOT
BMS
Booting Mode
1
0
Output
EPROM (Connect BMS to EPROM chip select)
0
0
1 (Input)
Host Processor
0
1
1 (Input)
Link Port
0
0
0 (Input)
No Booting. Processor executes from external memory.
0
1
0 (Input)
Reserved
1
1
x (Input)
Reserved
Timer Expired.
(Individual TIMEXP from y = SHARC_A, SHARC_B, SHARC_C, SHARC_D) Asserted
for four cycles when the timer is enabled and TCOUNT decrements to zero.
Clock In.
(Common to all SHARCs) External clock input to the AD14160/AD14160L. The instruction
cycle rate is equal to CLKIN. CLKIN may not be halted, changed, or operated below the minimum specified
frequency.
Module Reset.
(Common to all SHARCs) Resets the AD14160/AD14160L to a known state. This input
must be asserted (low) at power-up.
Test Clock (JTAG).
(Common to all SHARCs) Provides an asynchronous clock for JTAG boundary
scan.
Test Mode Select (JTAG).
(Common to all SHARCs) Used to control the test state machine. TMS has
a 20 k
internal pull-up resistor.
Test Data Input (JTAG).
Provides serial data for the boundary scan logic chain starting at SHARC_A.
TDI has a 20 k
internal pull-up resistor.
Test Data Output (JTAG).
Serial scan output of the boundary scan chain path, from SHARC_D.
Test Reset (JTAG).
(Common to all SHARCs) Resets the test state machine.
TRST
must be asserted
(pulsed low) after power-up or held low for proper operation of the AD14160/AD14160L.
TRST
has a
20 k
internal pull-up resistor.
Emulation Status.
(Common to all SHARCs) Must be connected to the ADSP-2106x EZ-ICE target
board connector
only
.
Power Supply.
Nominally +5.0 V dc for 5 V devices or +3.3 V dc for 3.3 V devices (50 pins).
Power Supply Return.
(64 pins).
TIMEXPy
O
CLKIN
I
RESET
I/A
TCK
I
TMS
I/S
TDI
I/S
TDO
TRST
O
I/A
EMU
(O/D)
O
V
DD
GND
P
G
NOTES
1
LINK PORTS 0 and 5 are connected internally as described earlier in Link Port I/O.
2
Three-statable only in EPROM boot mode (when
BMS
is an output).
相關(guān)PDF資料
PDF描述
AD14160BB-4 Quad-SHARC DSP Multiprocessor Family
AD14160L Quad-SHARC DSP Multiprocessor Family
AD14160LBB-4 ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86%
AD14160LKB-4 Quad-SHARC DSP Multiprocessor Family
AD1555-AD1556 24-Bit ADC WITH LOW NOISE PGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD14160BB-4 制造商:Rochester Electronics LLC 功能描述:- Bulk
AD14160KB-4 制造商:Rochester Electronics LLC 功能描述:- Bulk
AD14160L 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad-SHARC DSP Multiprocessor Family
AD14160LBB-4 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad-SHARC DSP Multiprocessor Family
AD14160LKB-4 制造商:Rochester Electronics LLC 功能描述:- Bulk
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