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參數(shù)資料
| 型號： | ACT-F512K32N-090P3T |
| 廠商： | Aeroflex Inc. |
| 英文描述： | 3-line to 8-line decoder / demultiplexer 16-SOIC 0 to 70 |
| 中文描述： | 行為F512K32高速16兆位閃存多芯片模塊 |
| 文件頁數(shù)： | 7/20頁 |
| 文件大小： | 238K |
| 代理商： | ACT-F512K32N-090P3T |
A
Aeroflex Circuit Technology
SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700
7
timer is reset. Any command other than sector erase
within the time-out window will reset the device to the
read mode, ignoring the previous command string.
Loading the sector erase buffer may be done in any
sequence and with any number of sectors (1 to 8).
Sector erase does not require the user to program the
device prior to erase. The device automatically
programs all memory locations in the sector(s) to be
erased prior to electrical erase. When erasing a sector
or sectors the remaining unselected sectors are not
affected. The system is not required to provide any
controls or timings during these operations. Post Erase
data state is all "1"s.
The automatic sector erase begins after the 80μs time
out from the rising edge of the WE pulse for the last
sector erase command pulse and terminates when the
data on D7 is “1" at which time the device returns to
read mode. During the execution of the Sector Erase
command, only the Erase Suspend and Erase Resume
commands are allowed. All other commands will reset
the device to read mode. Data Polling must be
performed at an address within any of the sectors being
erased.
Data Protection
The ACT-F512K32 is designed to offer protection
against accidental erasure or programming caused by
spurious system level singles that may exist during
power transitions. During power up the device
automatically resets the internal state machine in the
read mode. Also, with its control register architecture,
alteration of the memory content only occurs after
successful completion of specific multi-bus cycle
command sequences.
The device also incorporates several features to prevent
inadvertent write cycles resulting from Vcc power-up
and power-down transitions or system noise.
LOW V
cc
WRITE INHIBIT
To avoid initiation of a write cycle during Vcc power-up
and power-down, a write cycle is locked out for V
CC
less
than 3.2V (typically 3.7V). If V
CC
< V
LKO
, the command
register is disabled and all internal program/erase
circuits are disabled. Under this condition the device will
reset to read mode. Subsequent writes will be ignored
until the Vcc level is greater than V
LKO
. It is the users
responsibility to ensure that the control pins are logically
correct to prevent unintentional writes when Vcc is
above 3.2V.
WRITE PULSE GLITCH PROTECTION
Noise pulses of less than 5ns (typical) on OE, CE or
WE will not initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding anyone of OE = V
IL
, CE =
V
IH
or WE = V
IH
. To initiate a write cycle CE and WE
must be logical zero while OE is a logical one.
POWER-UP WRITE INHIBIT
Power-up of the device with WE = CE = V
IL
and OE =
V
IH
will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the
read mode on power-up.
Write Operation Status
D
7
DATA POLLING
The ACT-F512K32 features Data Polling as a method to
indicate to the host that the internal algorithms are in
progress or completed. During the program algorithm,
an attempt to read the device will produce compliment
data of the data last written to D
7
. During the erase
algorithm, an attempt to read the device will produce a
"0" at the D
7
Output. Upon completion of the erase
algorithm an attempt to read the device will produce a
"1" at the D
7
Output.
For chip Erase, the Data Polling is valid after the rising
edge of the sixth WE pulse in the six write pulse
sequence. For sector erase, the Data Polling is valid
after the last rising edge of the sector erase WE pulse.
Data polling must be performed at a sector address
within any of the sectors being erased and not a
protected sector. Otherwise, the status may not be valid.
Once the algorithm operation is close to being
completed, data pins (D
7
) change asynchronously while
the output enable (OE) is asserted low. This means that
the device is driving status information on D
7
at one
instance of time and then that byte's valid data at the
next instant of time. Depending on when the system
samples the D
7
Output, it may read the status or valid
data. Even if the device has completed internal
algorithm operation and D
7
has a valid data, the data
outputs on D
0
- D
6
may be still invalid. The valid data on
D0 - D
7
will be read on the successive read attempts.
The Data Polling feature is only active during the
programming algorithm, erase algorithm, or sector erase
time-out.
See Figures 6 and 10
D
6
TOGGLE BIT
The ACT-F512K32 also features the "Toggle Bit" as a
method to indicate to the host system that algorithms
are in progress or completed.
During a program or erase algorithm cycle, successive
attempts to read data from the device will result in D
6
toggling between one and zero. Once the program or
erase algorithm cycle is completed, D
6
Will stop toggling
and valid data will be read on successive attempts.
During programming the Toggle Bit is valid after the
rising edge of the fourth WE pulse in the four write pulse
sequence. For chip erase the Toggle Bit is valid after the
rising edge of the sixth
WE
pulse in the six write pulse
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相關代理商/技術參數(shù) |
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|---|---|
| ACT-F512K32N-090P7C | 制造商:AEROFLEX 制造商全稱:AEROFLEX 功能描述:ACT-F512K32 High Speed 16 Megabit FLASH Multichip Module |
| ACT-F512K32N-090P7I | 制造商:AEROFLEX 制造商全稱:AEROFLEX 功能描述:ACT-F512K32 High Speed 16 Megabit FLASH Multichip Module |
| ACT-F512K32N-090P7M | 制造商:AEROFLEX 制造商全稱:AEROFLEX 功能描述:ACT-F512K32 High Speed 16 Megabit FLASH Multichip Module |
| ACT-F512K32N-090P7Q | 制造商:AEROFLEX 制造商全稱:AEROFLEX 功能描述:ACT-F512K32 High Speed 16 Megabit FLASH Multichip Module |
| ACT-F512K32N-090P7T | 制造商:AEROFLEX 制造商全稱:AEROFLEX 功能描述:ACT-F512K32 High Speed 16 Megabit FLASH Multichip Module |
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