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參數(shù)資料
| 型號： | ACT-F512K32N-090P3T |
| 廠商： | Aeroflex Inc. |
| 英文描述： | 3-line to 8-line decoder / demultiplexer 16-SOIC 0 to 70 |
| 中文描述： | 行為F512K32高速16兆位閃存多芯片模塊 |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 238K |
| 代理商： | ACT-F512K32N-090P3T |
A
Aeroflex Circuit Technology
SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700
6
BYTE PROGRAMING
The device is programmed on a byte-byte basis.
Programming is a four bus cycle operation. There are
two "unlock" write cycles. These are followed by the
program set-up command and data write cycles.
Addresses are latched on the falling edge of CE or WE,
whichever occurs later, while the data is latched on the
rising edge of CE or WE whichever occurs first. The
rising edge of CE or WE (whichever occurs first) begins
programming. Upon executing the Embedded Program
Algorithm command sequence the system is not
required to provide further controls or timings. The
device will automatically provide adequate internally
generated program pulses and verify the programmed
cell margin. The automatic programming operation is
completed when the data on D
7
is equivalent to data
written to this bit at which time the device returns to the
read mode and addresses are no longer latched.
Therefore, the device requires that a valid address to the
device be supplied by the System at this time. Data
Polling must be performed at the memory location which
is being programmed.
Programming is allowed in any sequence and across
sector boundaries. Beware that a data "0" cannot be
programmed back to a “1". Attempting to do so may
cause the device to exceed programming time limits (D5
= 1) or result in an apparent success, according to the
data polling algorithm, but a read from reset/read mode
will show that the data is still “0". Only erase operations
can convert “0"s to “1"s.
Figure 3, 8 and 13 illustrates the programming algorithm
using typical command strings and bus operations.
CHIP ERASE
Chip erase is a six bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up" command. Two more"unlock" write cycles are
then followed by the chip erase command.
Chip erase does not require the user to program the
Embedded Erase Algorithm (Figure 4) sequence the
device automatically will program and verify the entire
memory for an all zero data pattern prior to electrical
erase. The chip erase is performed sequentially one
sector at a time. Note: Post Erase data state is all "1"s
The system is not required to provide any controls or
timings during these operations.
The automatic erase begins on the rising edge of the
last WE pulse in the command sequence and terminates
when the data in D7 is "1" (see Write Operation Status
section - Table 4) at which time the device returns to
read the mode. See Figures 4 and 9.
SECTOR ERASE
Sector erase is a six bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"setup" command. Two more "unlock" write cycles are
then followed by the sector erase command. The sector
address (any address location within the desired sector)
is latched on the falling edge of WE, while the command
(data) is latched on the rising edge of WE. A time-out of
80μs from the rising edge of the last sector erase
command will initiate the sector erase command(s).
Please note:
Do not attempt to write an invalid
command sequence during the sector erase operation.
otherwise, it wili terminate the sector erase operation
and the device will reset back into the read mode
Multiple sectors may be erased concurrently by writing
the six bus cycle operations as described above. This
sequence is followed with writes of the sector erase
command (30H) to addresses in other sectors desired to
be concurrently erased. The time between writes must
be less than 80μs, otherwise that command will not be
accepted. A time-out of 80μs from the rising edge of
the WE pulse for the last sector erase command will
initiate the sector erase. If another sector erase
command is written within the 80μs time-out window the
Table 3 — Commands Definitions
Command
Sequence
Bus
Write
Cycles
First Bus Write
Cycle
Second Bus Write
Cycle
Third Bus Write
Cycle
Fourth Bus
Read/Write Cycle
Fifth Bus Write
Cycle
Sixth Bus Write
Cycle
Required
Read/Reset
Read/Reset
Autoselect
Byte Program
Chip Erase
Sector Erase
Sector Erase Suspend
Sector Erase Resume
NOTES
:
1. Address bit A15, A16, A17 and A18 = X = Don't Care. Write Sequences may be initiated with A15 in either state.
2. Address bit A15, A16, A17 and A18 = X = Don't Care for all address commands except for Program Address (PA) and Sector Address (SA).
3. RA = Address of the memory location to be read
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse.
SA = Address of the sector to be erased. The combination of A18, A17, A16 will uniquely select any sector.
4. RD = Data read from location RA during read Operation.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE.
Addr
XXXH
5555H
5555H
5555H
5555H
5555H
Erase can be suspended during sector erase with Address (Don’t care), Data (B0H)
Erase can be resumed after suspend with Address (Don’t care), Data (30H)
Data
F0H
AAH
AAH
AAH
AAH
AAH
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
1
4
4
6
6
6
2AAAH
2AAAH
2AAAH
2AAAH
2AAAH
55H
55H
55H
55H
55H
5555H
5555H
5555H
5555H
5555H
F0H
90H
A0H
80H
80H
RA
RD
PA
PD
AAH
AAH
5555H
5555H
2AAAH
2AAAH
55H
55H
5555H
SA
10H
30H
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相關(guān)代理商/技術(shù)參數(shù) |
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| ACT-F512K32N-090P7C | 制造商:AEROFLEX 制造商全稱:AEROFLEX 功能描述:ACT-F512K32 High Speed 16 Megabit FLASH Multichip Module |
| ACT-F512K32N-090P7I | 制造商:AEROFLEX 制造商全稱:AEROFLEX 功能描述:ACT-F512K32 High Speed 16 Megabit FLASH Multichip Module |
| ACT-F512K32N-090P7M | 制造商:AEROFLEX 制造商全稱:AEROFLEX 功能描述:ACT-F512K32 High Speed 16 Megabit FLASH Multichip Module |
| ACT-F512K32N-090P7Q | 制造商:AEROFLEX 制造商全稱:AEROFLEX 功能描述:ACT-F512K32 High Speed 16 Megabit FLASH Multichip Module |
| ACT-F512K32N-090P7T | 制造商:AEROFLEX 制造商全稱:AEROFLEX 功能描述:ACT-F512K32 High Speed 16 Megabit FLASH Multichip Module |
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