參數(shù)資料
型號(hào)： ACT-F512K32N-090P3T
廠商： Aeroflex Inc.
英文描述： 3-line to 8-line decoder / demultiplexer 16-SOIC 0 to 70
中文描述： 行為F512K32高速16兆位閃存多芯片模塊
文件頁(yè)數(shù)： 5/20頁(yè)
文件大?。?/td> 238K
代理商： ACT-F512K32N-090P3T
A
Aeroflex Circuit Technology
SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700
5
Device Operation
The ACT-F512K32 MCM is composed of four, four
megabit Flash chips. The following description is for the
individual flash device, is applicable to each of the four
memory chips inside the MCM. Chip 1 is distinguished by
CE
1
and I/O
1-7
, Chip 2 by CE
2
and I/0
8-15
, Chip 3 by CE
3
and I/0
16-23
, and Chip 4 by CE
4
and I/0
24-31
.
Programming of the ACT-F512K32 is accomplished by
executing the program command sequence. The
program algorithm, which is an internal algorithm,
automatically times the program pulse widths and verifies
proper cell status. Sectors can be programed and
verified in less than one second. Erase is accomplished
by executing the erase command sequence. The erase
algorithm, which is internal, automatically preprograms
the array if it is not already programed before executing
the erase operation. During erase, the device
automatically times the erase pulse widths and verifies
proper cell status. The entire memory is typically erased
and verified in 1.5 seconds (if pre-programmed). The
sector mode allows for 64K byte blocks of memory to be
erased and reprogrammed without affecting other blocks.
Bus Operation
READ
The ACT-F512K32 has two control functions, both of
which must be logically active, to obtain data at the
outputs. Chip Enable (CE) is the power control and
should be used for device selection. Output-Enable (OE)
is the output control and should be used to gate data to
the output pins of the chip selected. Figure 7 illustrates
AC read timing waveforms.
OUTPUT DISABLE
With Output-Enable at a logic high level (V
IH
), output from
the device is disabled. Output pins are placed in a high
impedance state.
STANDBY MODE
The ACT-F512K32 standby mode consumes less than
6.5 mA. In the standby mode the outputs are in a high
impedance state, independent of the OE input.
If the device is deselected during erasure or
programming, the device will draw active current until the
operation is completed.
WRITE
Device erasure and programming are accomplished via
the command register. The contents of the register serve
as input to the internal state machine. The state machine
outputs dictate the function of the device.
The command register itself does not occupy an
addressable memory location. The register is a latch
used to store the command, along with address and data
information needed to execute the command. The
command register is written by bringing WE to a logic low
level (V
IL
), while CE is low and OE is at V
IH
. Addresses
are latched on the falling edge of WE or CE, whichever
happens later. Data is latched on the rising edge of the
WE or CE whichever occurs first. Standard
microprocessor write timings are used. Refer to AC
Program Characteristics and Waveforms, Figures 3,
8 and 13.
Command Definitions
Device operations are selected by writing specific
address and data sequences into the command register.
Table 3 defines these register command sequences.
READ/RESET COMMAND
The read or reset operation is initiated by writing the
read/reset command sequence into the command
register. Microprocessor read cycles retrieve array data
from the memory. The device remains enabled for reads
until the command register contents are altered.
The device will automatically power-up in the read/reset
state. In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will
retrieve array data. The device will automatically
power-up in the read/reset state. In this case, a
command sequence is not required to read data.
Standard Microprocessor read cycles will retrieve array
data. This default value ensures that no spurious
alteration of the memory content occurs during the power
transition. Refer to the AC Read Characteristics and
Figure 7 for the specific timing parameters.
Table 1 – Bus Operations
Operation
CE OE WE A0 A1 A6 A9
I/O
READ
L
L
H
A
0
A
1
A
6
A
9
DOUT
STANDBY
H
X
X
X
X
X
X
HIGH Z
OUTPUT DISABLE
L
H
H
X
X
X
X
HIGH Z
WRITE
L
H
L
A
0
A
1
A
6
A
9
D
IN
ENABLE SECTOR
PROTECT
L
V
ID
L
X
X
X
V
ID
X
VERIFY SECTOR
PROTECT
L
L
H
L
H
L
V
ID
Code
Table 2 – Sector Addresses Table
A18 A17
A16
Address Range
SA0
0
0
0
00000h – 0FFFFh
SA1
0
0
1
10000h – 1FFFFh
SA2
0
1
0
20000h – 2FFFFh
SA3
0
1
1
30000h – 3FFFFh
SA4
1
0
0
40000h – 4FFFFh
SA5
1
0
1
50000h – 5FFFFh
SA6
1
1
0
60000h – 6FFFFh
SA7
1
1
1
70000h – 7FFFFh
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