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參數(shù)資料
| 型號： | AAT1210 |
| 廠商： | Advanced Analog Technology,lnc. |
| 英文描述： | High Power DC/DC Boost Converter with Optional Dynamic Voltage Programming |
| 中文描述： | 高功率DC / DC升壓轉(zhuǎn)換器可選動態(tài)電壓編程 |
| 文件頁數(shù)： | 20/23頁 |
| 文件大?。?/td> | 707K |
| 代理商： | AAT1210 |
AAT1210
High Power DC/DC Boost Converter
with Optional Dynamic Voltage Programming
20
1210.2007.02.1.2
Table 6: S
2
Cwire Voltage Control Settings
(SEL = Low).
S
2
Cwire Serial Interface Timing
The S
2
Cwire serial interface has flexible timing.
Data can be clocked-in at speeds up to 1MHz.
After data has been submitted, EN/SET is held
high to latch the data for a period T
LAT
. The output
is subsequently changed to the predetermined volt-
age. When EN/SET is set low for a time greater
than T
OFF
, the AAT1210 is disabled. When dis-
abled, the register is reset to the default value,
which sets the FB2 pin to 0.6V if EN is subse-
quently pulled high.
PCB Layout
Boost converter performance can be adversely
affected by poor layout. Possible impact includes
high input and output voltage ripple, poor EMI per-
formance, and reduced operating efficiency. Every
attempt should be made to optimize the layout in
order to minimize parasitic PCB effects (stray
resistance, capacitance, inductance) and EMI cou-
pling from the high frequency SW node.
A suggested PCB layout for the AAT1210 boost
converter is shown in Figures 6, 7, and 8. The fol-
lowing PCB layout guidelines should be considered:
1.
Minimize the distance from Capacitor C1 and
C2 negative terminal to the PGND pins. This is
especially true with output capacitor C2, which
conducts high ripple current from the output
diode back to the PGND pins.
Place the feedback resistors close to the output
terminals. Route the output pin directly to resis-
tor R1 to maintain good output regulation. R3
should be routed close to the output GND pin,
but should not share a significant return path
with output capacitor C2.
Minimize the distance between L1 to D1 and
switching pin SW; minimize the size of the PCB
area connected to the SW pin.
Maintain a ground plane and connect to the IC
PGND pin(s) as well as the GND terminals of
C1 and C2.
Consider additional PCB area on D1 cathode
to maximize heatsinking capability. This may
be necessary when using a diode with a high
V
F
and/or thermal resistance.
To maximize thermal capacity, connect the
exposed paddle to the top and bottom power
planes using plated through vias. Top and bot-
tom planes should not extend far beyond the
TDFN34-16 package boundary to minimize
stray EMI.
2.
3.
4.
5.
6.
EN/SET
Rising
Edges
FB2
EN/SET
Rising
Edges
FB2
Reference
Voltage (V)
Reference
Voltage (V)
1
2
3
4
5
6
7
8
0.60 (Default)
0.64
0.68
0.72
0.76
0.80
0.84
0.88
9
10
11
12
13
14
15
16
0.92
0.96
1.00
1.04
1.08
1.12
1.16
1.20
Figure 5: S
2
Cwire Timing Diagram.
1
EN/SET
2
n-1
n
≤
16
Data Reg
0
n-1
0
T
HI
T
LO
T
LAT
T
OFF
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