
AAT1210
High Power DC/DC Boost Converter
with Optional Dynamic Voltage Programming
12
1210.2007.02.1.2
Increased load current results in a drop in the out-
put feedback voltage (FB1 or FB2) sensed through
the feedback resistors (R1, R2, R3 in Figure 2).
The controller responds by increasing the peak
inductor current, resulting in higher average current
in the inductor. Alternatively, decreased output load
results in an increase in the output feedback voltage.
The controller responds by decreasing the peak
inductor current, resulting in lower average current
in the inductor.
At light load, the inductor OFF interval current goes
below zero, which terminates the off period, and the
boost converter enters discontinuous mode opera-
tion. Further reduction in the load results in a corre-
sponding reduction in the switching frequency. The
AAT1210 provides optimized light load operation
which reduces switching losses and maintains the
highest possible efficiency at light load.
The AAT1210 switching frequency varies with
changes in the input voltage, output voltage, and
inductor size. Once the boost converter has
reached continuous mode, further increases in the
output load will not significantly change the operat-
ing frequency and constant ripple current in the
boost inductor is maintained.
Output Voltage Programming
The FB reference voltage is determined by the logic
state of the SEL pin. The output voltage is pro-
grammed through a resistor divider network (R1, R2,
R3) from the positive output terminal to FB1/FB2
pins to ground. Pulling the SELpin high activates the
FB1 pin which maintains a 1.2V reference voltage,
while the FB2 reference is disabled. Pulling the SEL
pin low activates the FB2 pin which maintains a 0.6V
reference, while the FB1 reference is disabled. The
FB1 and FB2 pins may be tied together when a stat-
ic DC output voltage is desired.
Toggling the SEL pin programs the output voltage
between two distinct output voltages across a 2.0X
range (maximum). With FB1, FB2 tied together, the
output voltage toggles between two voltages with a
2.0X scaling factor. An additional resistor between
FB1 and FB2 pins allows toggling between two
voltages with a <2.0X scaling factor.
Alternatively, the output voltage may be dynamical-
ly programmed to any of 16 voltage levels using the
S
2
Cwire serial digital input. The single-wire S
2
Cwire
interface provides high-speed output voltage pro-
grammability across a 2.0X output voltage range.
S
2
Cwire functionality is enabled by pulling the SEL
pin low and providing S
2
Cwire digital clock input to
the EN/SET pin which sets the FB2 voltage level
from 0.6V to 1.2V. Table 6 details the FB2 refer-
ence voltage versus S
2
Cwire rising clock edges.
Soft Start / Enable
The input disconnect switch is activated when a
valid input voltage is present and the EN/SET pin is
pulled high. The slew rate control on the P-channel
MOSFET ensures minimal inrush current as the
output voltage is charged to the input voltage, prior
to switching of the N-channel power MOSFET.
Monotonic turn-on is guaranteed by the integrated
soft-start circuitry.
Soft-start time of approximately 2.5ms is internally
programmed to minimize inrush current and elimi-
nate output voltage overshoot across the full input
voltage range under all loading conditions.
Current Limit and Over-Temperature
Protection
The switching of the N-channel MOSFET termi-
nates if the current limit of 3.0A (minimum) is
exceeded. This minimizes power dissipation and
component stresses under overload and short-cir-
cuit conditions. Switching resumes when the cur-
rent decays below the current limit.
Thermal protection disables the AAT1210 if internal
power dissipation becomes excessive. Thermal pro-
tection disables both the N-channel and P-channel
MOSFETs. The junction over-temperature threshold
is 140°C with 15°C of hysteresis. The output voltage
automatically recovers when the over-temperature
or over-current fault condition is removed.
Under-Voltage Lockout
Internal bias of all circuits is controlled via the VIN
input. Under-voltage lockout (UVLO) guarantees
sufficient V
IN
bias and proper operation of all inter-
nal circuitry prior to activation.