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參數(shù)資料
| 型號： | A8237 |
| 廠商： | Altera Corporation |
| 英文描述： | PROGRAMMABLE DMA CONTROLLER |
| 中文描述： | 可編程DMA控制器 |
| 文件頁數(shù)： | 9/22頁 |
| 文件大?。?/td> | 269K |
| 代理商： | A8237 |
Altera Corporation
13
a8237 Programmable DMA Controller Data Sheet
Request Register
The 4-bit request register allows software DMA requests. Hardware
requests (from
dreq
inputs) are masked by the mask register values;
software requests generated from the request register are unmaskable.
The request register request bits can only be programmed by the single
request bit command. The
reset
input or a master clear command clears
the request register. See
Table 5
.
Table 4. Mode Register Format
Bit
Description
1..0
00 = Channel 0 select
01 = Channel 1 select
10 = Channel 2 select
11 = Channel 3 select
11 during Read
00 = Verify transfer
01 = Write transfer
10 = Read transfer
11 = Illegal
0 = Auto-initialization disable
1 = Auto-initialization enable
0 = Address increment
1 = Address decrement
00 = Demand mode select
01 = Single mode select
10 = Block mode select
11 = Unused (Cascade mode is not supported.)
3..2
4
5
7..6
Table 5. Request Register Format
Bit
Description
0
1
2
3
1 = Channel 0 request
1 = Channel 1 request
1 = Channel 2 request
1 = Channel 3 request
1111
7..4
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