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參數(shù)資料
| 型號： | A8237 |
| 廠商： | Altera Corporation |
| 英文描述： | PROGRAMMABLE DMA CONTROLLER |
| 中文描述： | 可編程DMA控制器 |
| 文件頁數(shù)： | 16/22頁 |
| 文件大?。?/td> | 269K |
| 代理商： | A8237 |
20
Altera Corporation
a8237 Programmable DMA Controller Data Sheet
Auto-initialization
Auto-initialization allows each DMA channel to reinitialize after the
completion of a DMA cycle without microprocessor intervention. This
feature is enabled by setting bit 4 of each channel’s mode register. The
current address and current word count registers are loaded with the
values contained in the base address and base word count registers
following the normal or aborted (by the
neopin
signal) conclusion of a
DMA cycle.
Verify Transfer
The verify transfer type operates as a normal DMA read or write
operation, except that the I/O and memory control signals remain
deasserted. (The verify transfer type originated as a means to refresh
DRAM in early personal computers.)
Memory-to-Memory Transfer
The memory-to-memory DMA transfers are enabled via bit 0 of the
command register, and must be performed using channels 0 and 1. The
transfer is initiated by a software or hardware request on channel 0. At the
conclusion of the DMA cycle, the terminal count bit for channel 1 is set in
the status register, while the counterpart for channel 0 remains
unchanged. Also, channel 0 can be configured to hold the address
constant, allowing memory fills with a single data value.
Priority Encoding
The DMA requests are priority encoded to arbitrate between
simultaneous requests or multiple pending requests. Two modes of
priority encoding are available via bit 4 of the command register:
I
In fixed priority mode, the highest priority pending request is
selected, with channel 0 as the highest priority and channel 3 as the
lowest priority.
I
In rotating priority mode, the last channel to be serviced becomes the
lowest priority when selecting the next channel, with the other
channels rotating accordingly.
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